SoCEDSGettingStarted
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SoCEDSGettingStarted
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Introduction
This page contains a set of getting started guides to help users with getting started with Altera SoC EDS.
The currently covered version of SoC EDS is 16.1b196.
Getting Started with Board Setup
This section presents how to setup the Altera SoC Development board in order to use it with the getting started guides from this page.
Cyclone V Board (rev.E) Setup
Dual in-line package (DIP) Switch Settings:
| Switch | Setting |
|---|---|
| SW1 | all switches OFF |
| SW2 | all switches OFF |
| SW3 | ON-OFF-OFF-OFF-ON-ON |
| SW4 | OFF-OFF-ON-ON |
Jumper Settings:
| Switch | Description | Setting |
|---|---|---|
| J5 | 9V | Open |
| J6 | JTAG_HPS_SEL | Shorted |
| J7 | JTAG_SEL | Shorted |
| J9 | UART Signals | Open |
| J13 | OSC1_CLK_SEL | Shorted |
| J16 | JTAG_MIC_SEL | Open |
| J26 | CLKSEL0 | 2-3 Shorted |
| J27 | CLKSEL1 | 2-3 Shorted |
| J28 | BOOTSEL0 | 1-2 Shorted |
| J29 | BOOTSEL1 | 2-3 Shorted |
| J30 | BOOTSEL2 | 1-2 Shorted |
| J31 | SPI_I2C | Open |
External Connections:
- External 19V power supply connected to J22 – DC Input
- Mini USB cable connected from host PC to J37 – Altera USB Blaster II connector. This is used for connecting the host PC to the board for debugging purposes.
- Mini USB cable connected from host PC to J8 – UART USB connector. This is used for exporting the UART interface to the host PC.
- Ethernet cable from connector J2 to local network. This is used if Linux network connectivity is desired.
Arria V Board (rev. B) Setup
Arria 10 Board (rev. C) Setup
Memory Cards:
- Make sure DDR4 memory card is installed
- Make sure SD/MMC boot card is installed
Dip Switch Settings:
| Switch | Setting |
|---|---|
| SW1 | all OFF |
| SW2 | all OFF |
| SW3 | OFF-OFF-ON-ON-ON-OFF-OFF-OFF |
| SW4 | all OFF |
Jumper Settings:
- Place jumpers J16, J17,J32:9-10,J42:9-10
- Leave all other jumpers unplaced
External Connections:
- Make sure SW5 (power) is OFF
- Connect Micro USB cable from J22 to Host PC - for JTAG debugging
- Connect Mini USB cable from J10 to Host PC - for serial terminal connection
- Connect external 12V power supply to J36 (input power) connector
Getting Started with Running the Tools
This section presents how to run some of the tools provided with the SoC EDS.
Starting the Embedded Command Shell
The Embedded Command Shell is an utility that allows all the tools provided with the SoC EDS to be conveniently available from the command line interface.
The Embedded Command Shell can be started by using the following instructions:
- On Windows, go to Start > All Programs > Altera > SoC Embedded Design Suite > Embedded Command Shell,
- On Linux, run the script <SoC EDS installation directory>/embedded_command_shell.sh
Starting the ARM DS-5 AE Eclipse
This section presents how to start the ARM DS-5 AE Eclipse environment.
The required steps are:
1. Start an Embedded Command Shell (see 'Starting the Embedded Command Shell' section for details)
2. Start the ARM DS-5 AE Eclipse by running the command eclipse in the Embedded Command Shell.
3. Select a Workspace when asked to (you will need to have write permission to that folder) and press OK.
4. Eclipse will be started. The Welcome window allows access to useful getting started materials. If closed, the Welcome window can be re-opened by going to Help > Welcome to DS-5.
Getting Started with the Second Stage Bootloader
The Second Stage Bootloader (SSBL) is an essential tool for Altera SoC devices. It typically performs the low-level initialization, brings up SDRAM memory, loads the next boot stage from flash to SDRAM and executes it. On Cyclone V and Arria V SoC Devices the SSBL is also called "Preloader", while on Arria 10 SoC devices the SSBL is also called "Bootloader".
This section presents examples on how to generate and compile the SSBL for the Altera SoC Devices.
Generating and Compiling Cyclone V Preloader
This section presents an example of how to generate and compile the Preloader for the Cyclone V SoC Golden Hardware Reference Design (GHRD) that is provided with SoC EDS. The process for Arria V devices is very similar.
The Preloader is already delivered as part of the GHRD in the <SoC EDS installation directory>/examples/hardware/cv_soc_devkit_ghrd/software/preloader folder. In this example, you will re-create the Preloader in the folder <SoC EDS installation directory>/examples/hardware/cv_soc_devkit_ghrd/software/spl_bsp
The following pre-requisites are necessary in order to run the steps from this guide:
- Host PC running Windows or Linux
- SoC EDS 16.1b196+
The screenshots presented in this section were created using the Windows version of SoC EDS, but the example can be run in a very similar way on a Linux host PC.
The steps required to generate and build the default Preloader are:
1. Make sure the hardware design is compiled, so that the hardware-software handoff information is up to date. In our case this is already done, since the GHRD that is delivered with SoC EDS is already compiled.
2. Start an Embedded Command Shell (see 'Starting the Embedded Command Shell' section for details)
3. Start the BSP Editor by typing bsp-editor in the Embedded Command Shell.
4. Go to File > New HPS BSP .... This will open the New BSP dialog box.
5. In the New BSP dialog box, click the ... button and browse to the <SoCEDS folder>\examples\hardware\cv_soc_devkit_ghrd\hps_isw_handoff\soc_system_hps_0 folder which contains the hardware-software handoff folder. The rest of the settings in the New BSP Dialog box will be filled automatically with their default values.
6. Click OK to close the New BSP window. This will bring you back to the main BSP Editor window.
7. In the BSP Editor window the user can configure the Preloader. For this exercise, leave all settings at their default values, except making sure that SDRAM_SCRUBBING is checked.
8. Click Generate in the BSP Editor window to generate the Preloader files.
9. Click Exit in the BSP Editor window box to exit the application.
10. In the Embedded Command Shell, execute the following commands to build the Preloader
cd <SoC EDS installation directory>\examples\hardware\cv_soc_devkit_ghrd\software\spl_bsp
make
11. The Preloader will be compiled ready to be used in the above folder.
Some of the more relevant files that are created:
| File | Description |
|---|---|
| preloader-mkpimage.bin | Preloader with the proper header to be loaded by BootROM |
| uboot-socfpga\spl\u-boot-spl | Preloader ELF file, to be used for debugging purposes |
Generating and Compiling Arria 10 Bootloader
This section presents how to generate and compile the two available bootloader options for A10:
- U-Boot Bootloader
- UEFI Bootloader
Generating and Compiling Arria 10 U-Boot
This section presents an example of how to generate and compile the Bootloader for the Arria 10 SoC Golden Hardware Reference Design (GHRD) that is provided with SoC EDS.
The U-Bootis already delivered as part of the GHRD in the <SoC EDS installation directory>/examples/hardware/a10_soc_devkit_ghrd/software/bootloader folder. In this example, you will re-create the Bootloader in the folder <SoC EDS installation directory>/examples/hardware/a10_soc_devkit_ghrd/software/uboot_bsp
The following pre-requisites are necessary in order to run the steps from this guide:
- Host PC running Linux or Windows
- SoC EDS 16.1b196+
Note: U-Boot compilation is only supported on Linux host PCs. For both Windows and Linux, precompiled versions of U-Boot are provided, so this is not a limitation unless the user wants to edit the U-Boot source code, in which case a Linux host platform is needed.
The steps required to generate and build the default Bootloader are:
1. Make sure the hardware design is compiled, so that the hardware-software handoff information is up to date. In our case this is already done, since the GHRD that is delivered with SoC EDS is already compiled.
2. Start an Embedded Command Shell (see 'Starting the Embedded Command Shell' section for details)
3. Start the BSP Editor by running the command 'bsp-editor' in the Embedded Command Shell.
4. Go to File > New HPS BSP .... This will open the New BSP dialog box.
5. In the New BSP dialog box, click the ... button and browse to the <SoCEDS folder>\examples\hardware\a10_soc_devkit_ghrd\hps_isw_handoff folder which contains the hardware-software handoff folder. Select the Operating System to be U-Boot Bootloader (Arria 10 HPS). The rest of the settings in the New BSP Dialog box will be filled automatically with their default values.
6. Click OK to close the New BSP window. This will bring you back to the main BSP Editor window.
7. In the BSP Editor window the user can configure the Bootloader. For this exercise, leave all settings at their default values, except editing the rbf file names to match the ones needed already included with the precompiled GHRD:
8. Click Generate in the BSP Editor window to generate the Bootloader files.
9. Click Exit in the BSP Editor window box to exit the application.
10. In the Embedded Command Shell, execute the following commands to build the Bootloader.
cd <SoC EDS installation directory<\examples\hardware\a10_soc_devkit_ghrd\software\uboot_bsp
make
11. The U-Boot will be compiled ready to be used in the above folder.
Some of the more relevant files that are created:
| File | Description |
|---|---|
| uboot_w_dtb-mkpimage.bin | Combined U-Boot and U-Boot Device Tree Image, with the BootROM required header added |
| uboot-socfpga/u-boot | Bootloader ELF file, to be used for debugging purposes |
| devicetree.dtb | U-Boot Device Tree Binary, to be used for debugging purposes |
Generating and Compiling Arria 10 UEFI
This section presents an example of how to generate and compile the UEFI Bootloader for the Arria 10 SoC Golden Hardware Reference Design (GHRD) that is provided with SoC EDS.
The following pre-requisites are necessary in order to run the steps from this guide:
- Host PC running Linux or Windows
- SoC EDS 16.1b196+
Note: U-Boot compilation is only supported on Linux host PCs. For both Windows and Linux, precompiled versions of U-Boot are provided, so this is not a limitation unless the user wants to edit the U-Boot source code, in which case a Linux host platform is needed.
The steps required to generate and build the UEFI are:
1. Make sure the hardware design is compiled, so that the hardware-software handoff information is up to date. In our case this is already done, since the GHRD that is delivered with SoC EDS is already compiled.
2. Start an Embedded Command Shell (see 'Starting the Embedded Command Shell' section for details)
3. Start the BSP Editor by typing bsp-editor in the Embedded Command Shell.
4. Go to File > New HPS BSP .... This will open the New BSP dialog box.
5. In the New BSP dialog box, click the ... button and browse to the <SoCEDS folder>\examples\hardware\a10_soc_devkit_ghrd\hps_isw_handoff folder which contains the hardware-software handoff folder.
Select the Operating System to be UEFI Bootloader (Arria 10 HPS). The rest of the settings in the New BSP Dialog box will be filled automatically with their default values.
6. Click OK to close the New BSP window. This will bring you back to the main BSP Editor window.
7. In the BSP Editor window the user can configure the UEFI. For this exercise, leave all settings at their default values, except editing the rbf file names to match the ones needed already included with the precompiled GHRD:
8. Click Generate in the BSP Editor window to generate the UEFI Bootloader files.
9. Click Exit in the BSP Editor window box to exit the application.
10. In the Embedded Command Shell, execute the following commands to build the UEFI Bootloader.
cd <SoC EDS installation directory<\examples\hardware\a10_soc_devkit_ghrd\software\uefi_bsp
make
11. The UEFI will be compiled in the above folder.
Some of the more relevant files that are created:
| File | Description |
|---|---|
| uefi-socfpga/Build/PEI.ROM | Combined UEFI and UEFI Device Tree Image, with the BootROM required header added. Equivalent to uboot_w_dtb-mkpimage.bin. |
| devicetree.dtb | UEFI Device Tree Binary, to be used for debugging purposes |
Configuring FPGA from Cyclone V Preloader
The Cyclone V Preloader has the ability to configure the FPGA by using configuration data stored in one of the following two locations:
- specific address in QSPI Flash
- specific file name on a SD/MMC FAT Partition
In order to configure the FPGA, an RBF file needs to be used. The RBF file is obtained by converting a SOF file to RBF by using the Quartus II Programmer. Note: The options for generating the RBF file need to match the MSEL settings on the board.
RBF File Stored in QSPI Flash Memory
The following steps are required to enable the Preloader to configure the FPGA from an RBF file stored in QSPI Flash memory:
1. Configure the Preloader load the next boot stage from QSPI (Check BOOT_FROM_QSPI and uncheck the other BOOT_FROM options).
2. Generate Preloader.
3. Compile Preloader, to make sure all the source code is available.
4. Modify file <bsp directory>/uboot-socfpga/include/configs/socfpga_common.h to have the macro CONFIG_SPL_FPGA_LOAD defined. It is undefined by default.
5. If needed, edit the file <bsp directory>/uboot-socfpga/include/configs/socfpga_common.h to modify the CONFIG_SPL_FPGA_QSPI_ADDR macro to select a different location for the RBF data in flash.
6. Re-compile the Preloader and flash it to QSPI.
7. Wrap the RBF file with the mkimage header. This is used by the Preloader to determine the RBF file size. This can be achieved by using a command similar with the following:
mkimage -A arm -T standalone -C none -a 0 -e 0 -n "fpga image" -d <file.rbf> <file.img>
8. Program the wrapped RBF file to QSPI at the address CONFIG_SPL_FPGA_QSPI_ADDR.
9. Set up MSEL accordingly and boot board.
RBF File Stored on SD/MMC Card
The following steps are required to enable the Preloader to configure the FPGA from an RBF file stored on SD/MMC card:
1. Configure the Preloader load the next boot stage from SD/MMC (check BOOT_FROM_SDMMC and uncheck the other BOOT_FROM options).
2. Enable Preloader FAT Support (check FAT_SUPPORT).
3. Edit FAT_BOOT_PARTITION if necessary (default is "1").
4. Edit the FAT_LOAD_PAYLOAD_NAME if necessary (default is "u-boot.img").
5. Compile Preloader to make sure all the source code is available.
6. Modify file <bsp directory>/uboot-socfpga/include/configs/socfpga_common.h to have the macro CONFIG_SPL_FPGA_LOAD defined. It is undefined by default.
7. If needed, modify file <bsp directory>/uboot-socfpga/include/configs/socfpga_common.h to change the macro CONFIG_SPL_FPGA_FAT_NAME (the default is "fpga.rbf").
8. Re-compile the Preloader and write it to the SD card.
9. Write the RBF file to the selected FAT partition on the SD Card and using the selected file name.
10.Set up MSEL accordingly and boot board.
Getting Started with Basic Baremetal Development
This section demonstrates importing, compiling and debugging the Hello World bare-metal example application provided as part of SoC EDS.
Pre-requisites:
- Altera SoC Development Board (Cyclone V, Arria V or Arria 10)
- Host PC running Windows or Linux
- SoC EDS 16.1b196+
The screen snapshots and commands presented in this section were created using the Windows version of SoC EDS, but the example can be run in a very similar way on a Linux host PC.
Note: Make sure that Linux (or another OS) is not running on the board prior to doing this example. An OS can interfere with the feature of downloading and debugging bare-metal applications.
Sample Application Overview
The provided sample application prints a “Hello” message on the debugger console, by using semihosting. This way no pins are used and all communication happens through JTAG. The application is located in the On-Chip RAM, and therefore does not require the SDRAM memory on the board to be configured.
This application can run on any board supporting the SoC device because of its simplicity, and it does not require pins or external resources to be configured. Only 64KB of OCRAM is used, so the application is compatible with Cyclone V, Arria V and Arria 10.
Importing the Sample Application
1. Start Eclipse - (see 'starting the ARM DS-5 AE Eclipse' section for details)
2. Go to File > Import. The Import dialog box appears.
3. In the Import dialog box, select General > Existing Projects into Workspace and click Next. This will open the Import Projects dialog box
4. In the Import Projects dialog box, select the Select Archive File option.
5. Click Browse, then navigate to <SoC EDS installation directory>\embedded\examples\software\, select the file Altera-SoCFPGA-HelloWorld-Baremetal-GNU.tar.gz and click Open.
6. Click Finish. The project is imported. The project files are displayed in the Project Explorer panel.
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