cycloneIII_embedded_evaluation_kit_web_server_sopc

generated 2009.06.07.11:59:52

Overview

  osc_clk  cycloneIII_embedded_evaluation_kit_web_server_sopc
   tse_mac
 gm_rx_d  
 gm_rx_dv  
 gm_rx_err  
 gm_tx_d  
 gm_tx_en  
 gm_tx_err  
 m_rx_d  
 m_rx_en  
 m_rx_err  
 m_tx_d  
 m_tx_en  
 m_tx_err  
 m_rx_col  
 m_rx_crs  
 tx_clk  
 rx_clk  
 set_10  
 set_1000  
 ena_10  
 eth_mode  
 mdio_out  
 mdio_oen  
 mdio_in  
 mdc  
   button_pio
 in_port  
 out_port  
 bidir_port  
 out_port  
   touch_panel_spi
 MISO  
 MOSI  
 SCLK  
 SS_n  
   touch_panel_pen_irq_n
 in_port  
 out_port  
 out_port  
 bidir_port  
Processor
   cpu Nios II 9.0
Peripherals
   cpu altera_nios2 9.0
   flash_ssram_pipeline_bridge altera_avalon_pipeline_bridge 9.0
   pipeline_bridge_before_tristate_bridge altera_avalon_pipeline_bridge 9.0
   flash_ssram_tristate_bridge altera_avalon_tri_state_bridge 9.0
   ddr_sdram altmemddr 9.0
   cpu_ddr_clock_bridge altera_avalon_clock_crossing 9.0
   slow_peripheral_bridge altera_avalon_clock_crossing 9.0
   tse_mac triple_speed_ethernet 9.0
   sgdma_tx altera_avalon_sgdma 9.0
   sgdma_rx altera_avalon_sgdma 9.0
   tse_ddr_clock_bridge altera_avalon_clock_crossing 9.0
   tse_ssram_clock_bridge altera_avalon_clock_crossing 9.0
   descriptor_offset_bridge altera_avalon_pipeline_bridge 9.0
   descriptor_memory altera_avalon_onchip_memory2 9.0
   sys_clk_timer altera_avalon_timer 9.0
   performance_counter altera_avalon_performance_counter 9.0
   jtag_uart altera_avalon_jtag_uart 9.0
   sysid altera_avalon_sysid 9.0
   button_pio altera_avalon_pio 9.0
   led_pio altera_avalon_pio 9.0
   pio_id_eeprom_dat altera_avalon_pio 9.0
   pio_id_eeprom_scl altera_avalon_pio 9.0
   touch_panel_spi altera_avalon_spi 9.0
   touch_panel_pen_irq_n altera_avalon_pio 9.0
   pll altera_avalon_pll 9.0
   lcd_i2c_scl altera_avalon_pio 9.0
   lcd_i2c_en altera_avalon_pio 9.0
   lcd_i2c_sdat altera_avalon_pio 9.0
   remote_update altera_avalon_remote_update_cycloneiii 9.0
   lcd_sgdma altera_avalon_sgdma 9.0
   onchip_memory2_0 altera_avalon_onchip_memory2 9.0
cpu sgdma_tx sgdma_rx lcd_sgdma
 instruction_master  tightly_coupled_instruction_master_0  data_master  tightly_coupled_data_master_0  descriptor_read  descriptor_write  m_read  descriptor_read  descriptor_write  m_write  descriptor_read  descriptor_write  m_read
  cpu
jtag_debug_module  0x06000000 0x06000000
  ddr_sdram
s1  0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  tse_mac
control_port  0x08702800
  sgdma_tx
csr  0x08702400
  sgdma_rx
csr  0x08702000
  descriptor_memory
s1  0x0b000000 0x0b000000 0x0b000000 0x0b000000 0x0b000000
  sys_clk_timer
s1  0x08000100
  performance_counter
control_slave  0x08020000
  jtag_uart
avalon_jtag_slave  0x08002000
  sysid
control_slave  0x08000200
  button_pio
s1  0x08004000
  led_pio
s1  0x08005000
  pio_id_eeprom_dat
s1  0x08006000
  pio_id_eeprom_scl
s1  0x08007000
  touch_panel_spi
spi_control_port  0x08011000
  touch_panel_pen_irq_n
s1  0x08010000
  pll
s1  0x08200000
  lcd_i2c_scl
s1  0x08360200
  lcd_i2c_en
s1  0x08360000
  lcd_i2c_sdat
s1  0x08360100
  remote_update
s1  0x08610000
  lcd_sgdma
csr  0x02000000 0x02000000
  onchip_memory2_0
s1  0x06000800 s2  0x06000800

osc_clk

clock_source v9.0


Parameters

clockFrequency 50000000
clockFrequencyKnown true
  

Software Assignments

(none)

cpu

altera_nios2 v9.0
pll c0   cpu
  clk
data_master   flash_ssram_pipeline_bridge
  s1
instruction_master  
  s1
instruction_master   cpu_ddr_clock_bridge
  s1
data_master  
  s1
data_master   slow_peripheral_bridge
  s1
d_irq   sgdma_rx
  csr_irq
d_irq   sgdma_tx
  csr_irq
d_irq   sys_clk_timer
  irq
d_irq   jtag_uart
  irq
d_irq   button_pio
  irq
d_irq   touch_panel_pen_irq_n
  irq
d_irq   touch_panel_spi
  irq
d_irq   lcd_sgdma
  csr_irq
tightly_coupled_instruction_master_0   onchip_memory2_0
  s1
tightly_coupled_data_master_0  
  s2


Parameters

userDefinedSettings
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSetsPresent false
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_numShadowRegisterSets 1
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_eicPresent false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Automatic
setting_bit31BypassDCache true
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_autoAssignNumShadowRegisterSets true
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave ext_flash.s1
resetOffset 0
muldiv_multiplierType EmbeddedMulFast
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _4
mmu_udtlbNumEntries _6
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _10
mmu_enabled true
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave onchip_memory2_0.s1
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
impl Fast
icache_size _4096
icache_ramBlockType Automatic
icache_numTCIM _1
icache_burstType None
exceptionSlave ssram.s1
exceptionOffset 32
debug_triggerArming true
debug_level Level1
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _2048
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _1
dcache_lineSize _32
dcache_bursts false
cpuReset false
cpuID 0
clockFrequency 100000000
breakSlave cpu.jtag_debug_module
breakOffset 32
  

Software Assignments

CPU_IMPLEMENTATION "fast"
CPU_FREQ 100000000u
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 2048
INITDA_SUPPORTED
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
MMU_PRESENT
KERNEL_REGION_BASE 0xc0000000
IO_REGION_BASE 0xe0000000
KERNEL_MMU_REGION_BASE 0x80000000
USER_REGION_BASE 0x0
PROCESS_ID_NUM_BITS 10
TLB_NUM_WAYS 16
TLB_NUM_WAYS_LOG2 4
TLB_PTR_SZ 8
TLB_NUM_ENTRIES 256
FAST_TLB_MISS_EXCEPTION_ADDR 0xc6000800
EXCEPTION_ADDR 0xc5000020
RESET_ADDR 0xc4000000
BREAK_ADDR 0xc6000020
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
HAS_ILLEGAL_INSTRUCTION_EXCEPTION
HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION
HAS_EXTRA_EXCEPTION_INFO
CPU_ID_SIZE 1
CPU_ID_VALUE 0x0
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
INST_ADDR_WIDTH 27
DATA_ADDR_WIDTH 28

flash_ssram_pipeline_bridge

altera_avalon_pipeline_bridge v9.0
cpu data_master   flash_ssram_pipeline_bridge
  s1
instruction_master  
  s1
pll c0  
  clk
m1   pipeline_bridge_before_tristate_bridge
  s1


Parameters

burstEnable false
dataWidth 32
downstreamPipeline true
enableArbiterlock false
maxBurstSize 2
maximumPendingReadTransactions 10
slaveAddressWidth 23
upstreamPipeline true
waitrequestPipeline true
  

Software Assignments

(none)

pipeline_bridge_before_tristate_bridge

altera_avalon_pipeline_bridge v9.0
flash_ssram_pipeline_bridge m1   pipeline_bridge_before_tristate_bridge
  s1
pll c0  
  clk
tse_ssram_clock_bridge m1  
  s1
m1   flash_ssram_tristate_bridge
  avalon_slave
m1  
  avalon_slave


Parameters

burstEnable false
dataWidth 32
downstreamPipeline true
enableArbiterlock false
maxBurstSize 2
maximumPendingReadTransactions 7
slaveAddressWidth 23
upstreamPipeline true
waitrequestPipeline true
  

Software Assignments

(none)

flash_ssram_tristate_bridge

altera_avalon_tri_state_bridge v9.0
pipeline_bridge_before_tristate_bridge m1   flash_ssram_tristate_bridge
  avalon_slave
m1  
  avalon_slave
pll c0  
  clk
tristate_master   ssram
  s1
tristate_master   ext_flash
  s1


Parameters

registerIncomingSignals true
  

Software Assignments

(none)

ssram

altera_avalon_cy7c1380_ssram v9.0
flash_ssram_tristate_bridge tristate_master   ssram
  s1
pll c0  
  clk


Parameters

readLatency 2
sharedPorts s1/address,s1/data
simMakeModel true
size 1
  

Software Assignments

SRAM_MEMORY_SIZE 1
SRAM_MEMORY_UNITS 1048576
SSRAM_DATA_WIDTH 32
SSRAM_READ_LATENCY 2

ext_flash

altera_avalon_cfi_flash v9.0
flash_ssram_tristate_bridge tristate_master   ext_flash
  s1
pll c0  
  clk


Parameters

actualHoldTime 20.0
actualSetupTime 30.0
actualWaitTime 70.0
addressWidth 23
clockRate 100000000
corePreset INTEL128P30
dataWidth 16
holdTime 20
setupTime 25
sharedPorts s1/address,s1/data
timingUnits NS
waitTime 70
  

Software Assignments

SETUP_VALUE 25
WAIT_VALUE 70
HOLD_VALUE 20
TIMING_UNITS "ns"
SIZE 16777216u

ddr_sdram

altmemddr v9.0
osc_clk clk   ddr_sdram
  refclk
cpu_ddr_clock_bridge m1  
  s1
tse_ddr_clock_bridge m1  
  s1
lcd_sgdma descriptor_read  
  s1
descriptor_write  
  s1
m_read  
  s1
sysclk   cpu_ddr_clock_bridge
  clk_m1
sysclk   tse_ddr_clock_bridge
  clk_m1
sysclk   lcd_sgdma
  clk
sysclk   lcd_ta_sgdma_to_fifo
  clk
sysclk   lcd_pixel_fifo
  clk_in


Parameters

pipeline_commands false
debug_en false
export_debug_port false
use_generated_memory_model true
dedicated_memory_clk_phase_label Dedicated memory clock phase:
mem_if_clk_mhz 133.0
quartus_project_exists false
local_if_drate Half
enable_v72_rsu false
local_if_clk_mhz_label (66.5 MHz)
new_variant true
mem_if_memtype DDR SDRAM
pll_ref_clk_mhz 50.0
mem_if_clk_ps_label (7519 ps)
family Cyclone III
project_family Cyclone III
speed_grade 8
dedicated_memory_clk_phase 0
pll_ref_clk_ps_label (20000 ps)
avalon_burst_length 1
WIDTH_RATIO 4
mem_if_pchaddr_bit 10
mem_if_clk_pair_count 1
vendor Other
chip_or_dimm Discrete Device
mem_fmax 200.0
mem_if_cs_per_dimm 1
pre_latency_label Fix read latency at:
dedicated_memory_clk_en false
mirror_addressing 0
mem_if_bankaddr_width 2
mem_if_preset_rlat 0
post_latency_label cycles (0 cycles=minimum latency, non-deterministic)
mem_dyn_deskew_en false
mem_if_cs_width 1
mem_if_rowaddr_width 13
local_if_dwidth_label 64
mem_if_dm_pins_en Yes
mem_if_preset PSC A2S56D40CTP-G5
fast_simulation_en FAST
mem_if_coladdr_width 9
mem_if_dq_per_dqs 8
mem_if_dwidth 16
mem_tiha_ps 600
mem_tdsh_ck 0.2
mem_if_trfc_ns 70.0
mem_tqh_ck 0.36
mem_tisa_ps 600
mem_tdss_ck 0.2
mem_if_tinit_us 200.0
mem_if_trcd_ns 15.0
mem_if_twtr_ck 2
mem_tdqss_ck 0.28
mem_tqhs_ps 500
mem_tdsa_ps 400
mem_tac_ps 700
mem_tdha_ps 400
mem_if_tras_ns 40.0
mem_if_twr_ns 15.0
mem_tdqsck_ps 550
mem_if_trp_ns 15.0
mem_tdqsq_ps 400
mem_if_tmrd_ns 10.0
mem_if_trefi_us 7.0
mem_tcl 3.0
mem_tcl_40_fmax 533.0
mem_odt Disabled
mem_dll_en Yes
ac_phase 90
mem_drv_str Normal
mem_if_oct_en false
input_period 0
mem_tcl_60_fmax 533.0
board_skew_ps 20
mem_if_dqsn_en false
dll_external false
mem_tcl_15_fmax 533.0
mem_tcl_30_fmax 200.0
mem_bl 4
ac_clk_select 90
mem_tcl_50_fmax 533.0
mem_tcl_25_fmax 200.0
mem_tcl_20_fmax 133.333
pll_reconfig_ports_en false
mem_btype Sequential
ctl_ecc_en false
user_refresh_en false
local_if_type_avalon true
ctl_self_refresh_en false
clk_source_sharing_en false
phy_if_type_afi false
ctl_autopch_en false
shared_sys_clk_source
ref_clk_source osc_clk
ctl_powerdn_en false
tool_context SOPC_BUILDER
mem_srtr Normal
mem_mpr_loc Predefined Pattern
dss_tinit_rst_us 200.0
mem_tcl_90_fmax 400.0
mem_rtt_wr Dynamic ODT off
mem_tcl_100_fmax 400.0
mem_pasr Full Array
mem_asrm Manual SR Reference (SRT)
mem_mpr_oper Predefined Pattern
mem_tcl_80_fmax 400.0
mem_drv_impedance RZQ/7
mem_rtt_nom ODT Disabled
mem_tcl_70_fmax 400.0
mem_wtcl 5.0
mem_dll_pch Fast Exit
mem_atcl Disabled
  

Software Assignments

(none)

cpu_ddr_clock_bridge

altera_avalon_clock_crossing v9.0
cpu instruction_master   cpu_ddr_clock_bridge
  s1
data_master  
  s1
pll c0  
  clk_s1
ddr_sdram sysclk  
  clk_m1
m1   ddr_sdram
  s1
m1   lcd_sgdma
  csr


Parameters

dataWidth 32
downstreamFIFODepth 8
downstreamUseRegister false
masterSyncDepth 3
maxBurstSize 8
slaveAddressWidth 24
slaveSyncDepth 3
upstreamFIFODepth 64
upstreamUseRegister false
useBurstCount false
  

Software Assignments

(none)

slow_peripheral_bridge

altera_avalon_clock_crossing v9.0
pll c0   slow_peripheral_bridge
  clk_s1
c2  
  clk_m1
cpu data_master  
  s1
m1   pll
  s1
m1   descriptor_memory
  s1
m1   sgdma_rx
  csr
m1   sgdma_tx
  csr
m1   tse_mac
  control_port
m1   sys_clk_timer
  s1
m1   performance_counter
  control_slave
m1   jtag_uart
  avalon_jtag_slave
m1   sysid
  control_slave
m1   button_pio
  s1
m1   led_pio
  s1
m1   pio_id_eeprom_dat
  s1
m1   pio_id_eeprom_scl
  s1
m1   touch_panel_pen_irq_n
  s1
m1   touch_panel_spi
  spi_control_port
m1   lcd_i2c_en
  s1
m1   lcd_i2c_scl
  s1
m1   lcd_i2c_sdat
  s1
m1   remote_update
  s1


Parameters

dataWidth 32
downstreamFIFODepth 16
downstreamUseRegister false
masterSyncDepth 3
maxBurstSize 8
slaveAddressWidth 24
slaveSyncDepth 3
upstreamFIFODepth 64
upstreamUseRegister false
useBurstCount false
  

Software Assignments

(none)

tse_mac

triple_speed_ethernet v9.0
pll c2   tse_mac
  receive_clock_connection
c2  
  transmit_clock_connection
c2  
  control_port_clock_connection
slow_peripheral_bridge m1  
  control_port
sgdma_tx out  
  transmit
receive   sgdma_rx
  in


Parameters

atlanticSinkClockRate 0
atlanticSinkClockSource pll
atlanticSourceClockRate 0
atlanticSourceClockSource pll
avalonSlaveClockRate 0
avalonSlaveClockSource pll
avalonStNeighbours {TRANSMIT=sgdma_tx, RECEIVE=sgdma_rx}
channel_count 1
core_variation MAC_ONLY
core_version 2304
crc32check16bit 0
crc32dwidth 8
crc32gendelay 6
crc32s1l2_extern false
cust_version 1
dataBitsPerSymbol 8
dev_version 2304
deviceFamily CYCLONEIII
eg_addr 9
eg_fifo 512
ena_hash false
enable_alt_reconfig false
enable_clk_sharing false
enable_ena 32
enable_fifoless false
enable_gmii_loopback false
enable_hd_logic true
enable_mac_flow_ctrl false
enable_mac_txaddr_set true
enable_mac_vlan false
enable_maclite false
enable_magic_detect false
enable_multi_channel false
enable_pkt_class true
enable_pma false
enable_reg_sharing false
enable_sgmii false
enable_shift16 true
enable_sup_addr false
enable_use_internal_fifo true
export_calblkclk false
export_pwrdn false
ext_stat_cnt_ena false
gigeAdvanceMode false
ifGMII MII_GMII
ifPCSuseEmbeddedSerdes false
ing_addr 9
ing_fifo 512
insert_ta true
maclite_gige false
max_channels 1
mdio_clk_div 40
phy_identifier 0
ramType AUTO
reset_level 1
sopcSystemTopLevelName cycloneIII_embedded_evaluation_kit_web_server_sopc
stat_cnt_ena true
timingAdapterName sgdma_rx
toolContext SOPC_BUILDER
transceiver_type GXB
uiEgFIFOSize 512 x 32 Bits
uiHostClockFrequency 0
uiIngFIFOSize 512 x 32 Bits
uiMACFIFO false
uiMACOptions false
uiMDIOFreq 0.0 MHz
uiMIIInterfaceOptions false
uiPCSInterface false
uiPCSInterfaceOptions false
useLvds false
useMAC true
useMDIO true
usePCS false
use_sync_reset false
  

Software Assignments

TRANSMIT "sgdma_tx"
RECEIVE "sgdma_rx"
TRANSMIT_FIFO_DEPTH 512
RECEIVE_FIFO_DEPTH 512
FIFO_WIDTH 32
ENABLE_MACLITE 0
MACLITE_GIGE 0
USE_MDIO 1
NUMBER_OF_CHANNEL 1
NUMBER_OF_MAC_MDIO_SHARED 1
IS_MULTICHANNEL_MAC 0
MDIO_SHARED 0
REGISTER_SHARED 0
PCS 0
PCS_SGMII 0
PCS_ID 0u

sgdma_tx

altera_avalon_sgdma v9.0
pll c2   sgdma_tx
  clk
slow_peripheral_bridge m1  
  csr
cpu d_irq  
  csr_irq
descriptor_read   descriptor_offset_bridge
  s1
descriptor_write  
  s1
m_read   tse_ssram_clock_bridge
  s1
m_read   tse_ddr_clock_bridge
  s1
out   tse_mac
  transmit


Parameters

actualDataTransferFIFODepth 64
addressWidth 32
alwaysDoMaxBurst true
dataTransferFIFODepth 2
enableBurstTransfers false
enableDescriptorReadMasterBurst false
enableUnalignedTransfers false
internalFIFODepth 2
readBlockDataWidth 32
readBurstcountWidth 4
sinkErrorWidth 0
sourceErrorWidth 1
transferMode MEMORY_TO_STREAM
writeBurstcountWidth 4
  

Software Assignments

READ_BLOCK_DATA_WIDTH 32
WRITE_BLOCK_DATA_WIDTH 32
STREAM_DATA_WIDTH 32
ADDRESS_WIDTH 32
HAS_READ_BLOCK 1
HAS_WRITE_BLOCK 0
READ_BURSTCOUNT_WIDTH 4
WRITE_BURSTCOUNT_WIDTH 4
BURST_TRANSFER 0
ALWAYS_DO_MAX_BURST 1
DESCRIPTOR_READ_BURST 0
UNALIGNED_TRANSFER 0
CONTROL_SLAVE_DATA_WIDTH 32
CONTROL_SLAVE_ADDRESS_WIDTH 8
DESC_DATA_WIDTH 32
CHAIN_WRITEBACK_DATA_WIDTH 32
STATUS_TOKEN_DATA_WIDTH 24
BYTES_TO_TRANSFER_DATA_WIDTH 16
BURST_DATA_WIDTH 8
CONTROL_DATA_WIDTH 8
ATLANTIC_CHANNEL_DATA_WIDTH 4
COMMAND_FIFO_DATA_WIDTH 104
SYMBOLS_PER_BEAT 4
IN_ERROR_WIDTH 0
OUT_ERROR_WIDTH 1

sgdma_rx

altera_avalon_sgdma v9.0
pll c2   sgdma_rx
  clk
slow_peripheral_bridge m1  
  csr
cpu d_irq  
  csr_irq
tse_mac receive  
  in
descriptor_read   descriptor_offset_bridge
  s1
descriptor_write  
  s1
m_write   tse_ssram_clock_bridge
  s1
m_write   tse_ddr_clock_bridge
  s1


Parameters

actualDataTransferFIFODepth 64
addressWidth 32
alwaysDoMaxBurst true
dataTransferFIFODepth 2
enableBurstTransfers false
enableDescriptorReadMasterBurst false
enableUnalignedTransfers false
internalFIFODepth 2
readBlockDataWidth 32
readBurstcountWidth 4
sinkErrorWidth 6
sourceErrorWidth 0
transferMode STREAM_TO_MEMORY
writeBurstcountWidth 4
  

Software Assignments

READ_BLOCK_DATA_WIDTH 32
WRITE_BLOCK_DATA_WIDTH 32
STREAM_DATA_WIDTH 32
ADDRESS_WIDTH 32
HAS_READ_BLOCK 0
HAS_WRITE_BLOCK 1
READ_BURSTCOUNT_WIDTH 4
WRITE_BURSTCOUNT_WIDTH 4
BURST_TRANSFER 0
ALWAYS_DO_MAX_BURST 1
DESCRIPTOR_READ_BURST 0
UNALIGNED_TRANSFER 0
CONTROL_SLAVE_DATA_WIDTH 32
CONTROL_SLAVE_ADDRESS_WIDTH 8
DESC_DATA_WIDTH 32
CHAIN_WRITEBACK_DATA_WIDTH 32
STATUS_TOKEN_DATA_WIDTH 24
BYTES_TO_TRANSFER_DATA_WIDTH 16
BURST_DATA_WIDTH 8
CONTROL_DATA_WIDTH 8
ATLANTIC_CHANNEL_DATA_WIDTH 4
COMMAND_FIFO_DATA_WIDTH 104
SYMBOLS_PER_BEAT 4
IN_ERROR_WIDTH 6
OUT_ERROR_WIDTH 0

tse_ddr_clock_bridge

altera_avalon_clock_crossing v9.0
pll c2   tse_ddr_clock_bridge
  clk_s1
ddr_sdram sysclk  
  clk_m1
sgdma_rx m_write  
  s1
sgdma_tx m_read  
  s1
m1   ddr_sdram
  s1


Parameters

dataWidth 32
downstreamFIFODepth 8
downstreamUseRegister false
masterSyncDepth 3
maxBurstSize 8
slaveAddressWidth 23
slaveSyncDepth 3
upstreamFIFODepth 64
upstreamUseRegister false
useBurstCount false
  

Software Assignments

(none)

tse_ssram_clock_bridge

altera_avalon_clock_crossing v9.0
pll c2   tse_ssram_clock_bridge
  clk_s1
c0  
  clk_m1
sgdma_rx m_write  
  s1
sgdma_tx m_read  
  s1
m1   pipeline_bridge_before_tristate_bridge
  s1


Parameters

dataWidth 32
downstreamFIFODepth 16
downstreamUseRegister false
masterSyncDepth 3
maxBurstSize 8
slaveAddressWidth 23
slaveSyncDepth 3
upstreamFIFODepth 64
upstreamUseRegister false
useBurstCount false
  

Software Assignments

(none)

descriptor_offset_bridge

altera_avalon_pipeline_bridge v9.0
pll c2   descriptor_offset_bridge
  clk
sgdma_rx descriptor_read  
  s1
descriptor_write  
  s1
sgdma_tx descriptor_read  
  s1
descriptor_write  
  s1
m1   descriptor_memory
  s1


Parameters

burstEnable false
dataWidth 256
downstreamPipeline true
enableArbiterlock false
maxBurstSize 2
maximumPendingReadTransactions 4
slaveAddressWidth 21
upstreamPipeline true
waitrequestPipeline true
  

Software Assignments

(none)

descriptor_memory

altera_avalon_onchip_memory2 v9.0
pll c2   descriptor_memory
  clk1
slow_peripheral_bridge m1  
  s1
descriptor_offset_bridge m1  
  s1


Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
dualPort false
initMemContent true
initializationFileName descriptor_memory
instanceID NONE
memorySize 4096
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "descriptor_memory"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SIZE_VALUE 4096u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

sys_clk_timer

altera_avalon_timer v9.0
slow_peripheral_bridge m1   sys_clk_timer
  s1
cpu d_irq  
  irq
pll c2  
  clk


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 10.0
periodUnits MSEC
resetOutput false
snapshot true
systemFrequency 60000000
timeoutPulseOutput false
timerPreset FULL_FEATURED
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 10.0
PERIOD_UNITS "ms"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 60000000u
LOAD_VALUE 599999ULL
COUNTER_SIZE 32
MULT 0.0010
TICKS_PER_SEC 100u

performance_counter

altera_avalon_performance_counter v9.0
slow_peripheral_bridge m1   performance_counter
  control_slave
pll c2  
  clk


Parameters

numberOfSections 1
  

Software Assignments

HOW_MANY_SECTIONS 1

jtag_uart

altera_avalon_jtag_uart v9.0
slow_peripheral_bridge m1   jtag_uart
  avalon_jtag_slave
cpu d_irq  
  irq
pll c2  
  clk


Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 8
readIRQThreshold 4
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer true
useRegistersForWriteBuffer true
writeBufferDepth 8
writeIRQThreshold 4
  

Software Assignments

WRITE_DEPTH 8
READ_DEPTH 8
WRITE_THRESHOLD 4
READ_THRESHOLD 4

sysid

altera_avalon_sysid v9.0
slow_peripheral_bridge m1   sysid
  control_slave
pll c2  
  clk


Parameters

id 84075349
timestamp 1244347165
  

Software Assignments

ID 84075349u
TIMESTAMP 1244347165u

button_pio

altera_avalon_pio v9.0
slow_peripheral_bridge m1   button_pio
  s1
pll c2  
  clk
cpu d_irq  
  irq


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 60000000
direction Input
edgeType RISING
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring true
simDrivenValue 15
width 4
  

Software Assignments

DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0xf
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 4
RESET_VALUE 0x0
EDGE_TYPE "RISING"
IRQ_TYPE "EDGE"
FREQ 60000000u

led_pio

altera_avalon_pio v9.0
slow_peripheral_bridge m1   led_pio
  s1
pll c2  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 60000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 2
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 2
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 60000000u

pio_id_eeprom_dat

altera_avalon_pio v9.0
slow_peripheral_bridge m1   pio_id_eeprom_dat
  s1
pll c2  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 60000000
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 1
HAS_OUT 0
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 60000000u

pio_id_eeprom_scl

altera_avalon_pio v9.0
slow_peripheral_bridge m1   pio_id_eeprom_scl
  s1
pll c2  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 60000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 60000000u

touch_panel_spi

altera_avalon_spi v9.0
slow_peripheral_bridge m1   touch_panel_spi
  spi_control_port
cpu d_irq  
  irq
pll c2  
  clk


Parameters

actualClockRate 31982.0
actualSlaveSelectToSClkDelay 0.0
clockPhase 0
clockPolarity 0
dataWidth 8
inputClockRate 60000000
insertDelayBetweenSlaveSelectAndSClk false
lsbOrderedFirst false
masterSPI true
numberOfSlaves 1
targetClockRate 32000
targetSlaveSelectToSClkDelay 0.0
  

Software Assignments

DATABITS 8
DATAWIDTH 16
TARGETCLOCK 32000u
CLOCKUNITS "Hz"
CLOCKMULT 1
NUMSLAVES 1
ISMASTER 1
CLOCKPOLARITY 0
CLOCKPHASE 0
LSBFIRST 0
EXTRADELAY 0
TARGETSSDELAY "0.0"
DELAYUNITS "ns"
DELAYMULT "1.0E-9"
PREFIX "spi_"

touch_panel_pen_irq_n

altera_avalon_pio v9.0
slow_peripheral_bridge m1   touch_panel_pen_irq_n
  s1
pll c2  
  clk
cpu d_irq  
  irq


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 60000000
direction Input
edgeType FALLING
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "FALLING"
IRQ_TYPE "EDGE"
FREQ 60000000u

pll

altera_avalon_pll v9.0
slow_peripheral_bridge m1   pll
  s1
osc_clk clk  
  inclk0
c0   flash_ssram_pipeline_bridge
  clk
c0   pipeline_bridge_before_tristate_bridge
  clk
c0   flash_ssram_tristate_bridge
  clk
c0   ssram
  clk
c0   ext_flash
  clk
c0   cpu_ddr_clock_bridge
  clk_s1
c0   slow_peripheral_bridge
  clk_s1
c2  
  clk_m1
c2   tse_ddr_clock_bridge
  clk_s1
c2   tse_ssram_clock_bridge
  clk_s1
c0  
  clk_m1
c2   descriptor_memory
  clk1
c2   sgdma_rx
  clk
c2   sgdma_tx
  clk
c2   tse_mac
  receive_clock_connection
c2  
  transmit_clock_connection
c2  
  control_port_clock_connection
c2   descriptor_offset_bridge
  clk
c2   sys_clk_timer
  clk
c2   performance_counter
  clk
c2   jtag_uart
  clk
c2   sysid
  clk
c2   button_pio
  clk
c2   led_pio
  clk
c2   pio_id_eeprom_dat
  clk
c2   pio_id_eeprom_scl
  clk
c2   touch_panel_pen_irq_n
  clk
c2   touch_panel_spi
  clk
c2   lcd_i2c_en
  clk
c2   lcd_i2c_scl
  clk
c2   lcd_i2c_sdat
  clk
c0   cpu
  clk
c3   remote_update
  global_signals_clock
c0   lcd_pixel_fifo
  clk_out
c0   lcd_ta_fifo_to_dfa
  clk
c0   lcd_64_to_32_bits_dfa
  clk
c0   lcd_pixel_converter
  clk
c0   lcd_32_to_8_bits_dfa
  clk
c0   lcd_sync_generator
  clk
c0   onchip_memory2_0
  clk1
c0  
  clk2


Parameters

c0 tap c0 mult 2 div 1 phase 0 enabled true inputfreq 50000000 outputfreq 100000000
c1 tap c1 mult 2 div 1 phase -2000 enabled true inputfreq 50000000 outputfreq 100000000
c2 tap c2 mult 6 div 5 phase 0 enabled true inputfreq 50000000 outputfreq 60000000
c3 tap c3 mult 4 div 5 phase 0 enabled true inputfreq 50000000 outputfreq 40000000
c4 tap c4 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c5 tap c5 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c6 tap c6 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c7 tap c7 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c8 tap c8 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c9 tap c9 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
deviceFamily CYCLONEIII
e0 tap e0 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
e1 tap e1 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
e2 tap e2 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
e3 tap e3 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
inputClockFrequency 50000000
inputClockRate 50000000
lockedOutputPortOption Export
pfdenaInputPortOption Register
pllHdl // megafunction wizard: %ALTPLL% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altpll // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" // Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1" // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.0" // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" // Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" // Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" // Retrieval info: PRIVATE: SPREAD_USE STRING "0" // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" // Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" // Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION" // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_enable0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_enable1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_extclkena0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_extclkena1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_extclkena2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_extclkena3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_sclkout0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_sclkout1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0" // Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT NUMERIC "0.0" // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT NUMERIC "-2000.0" // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "6" // Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5" // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT NUMERIC "0.0" // Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4" // Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "5" // Retrieval info: CONSTANT: CLK3_PHASE_SHIFT NUMERIC "0.0" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
resetInputPortOption Register
  

Software Assignments

ARESET "None"
PFDENA "None"
LOCKED "None"
PLLENA "None"
SCANCLK "None"
SCANDATA "None"
SCANREAD "None"
SCANWRITE "None"
SCANCLKENA "None"
SCANACLR "None"
SCANDATAOUT "None"
SCANDONE "None"
CONFIGUPDATE "None"
PHASECOUNTERSELECT "None"
PHASEDONE "None"
PHASEUPDOWN "None"
PHASESTEP "None"

lcd_i2c_scl

altera_avalon_pio v9.0
slow_peripheral_bridge m1   lcd_i2c_scl
  s1
pll c2  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 60000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 60000000u

lcd_i2c_en

altera_avalon_pio v9.0
slow_peripheral_bridge m1   lcd_i2c_en
  s1
pll c2  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 60000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 60000000u

lcd_i2c_sdat

altera_avalon_pio v9.0
slow_peripheral_bridge m1   lcd_i2c_sdat
  s1
pll c2  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 60000000
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 1
HAS_OUT 0
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 60000000u

remote_update

altera_avalon_remote_update_cycloneiii v9.0
slow_peripheral_bridge m1   remote_update
  s1
pll c3  
  global_signals_clock


Parameters

(none)
  

Software Assignments

(none)

lcd_sgdma

altera_avalon_sgdma v9.0
cpu_ddr_clock_bridge m1   lcd_sgdma
  csr
cpu d_irq  
  csr_irq
ddr_sdram sysclk  
  clk
descriptor_read   ddr_sdram
  s1
descriptor_write  
  s1
m_read  
  s1
out   lcd_ta_sgdma_to_fifo
  in


Parameters

actualDataTransferFIFODepth 32
addressWidth 32
alwaysDoMaxBurst true
dataTransferFIFODepth 2
enableBurstTransfers false
enableDescriptorReadMasterBurst false
enableUnalignedTransfers false
internalFIFODepth 2
readBlockDataWidth 64
readBurstcountWidth 4
sinkErrorWidth 0
sourceErrorWidth 0
transferMode MEMORY_TO_STREAM
writeBurstcountWidth 4
  

Software Assignments

READ_BLOCK_DATA_WIDTH 64
WRITE_BLOCK_DATA_WIDTH 64
STREAM_DATA_WIDTH 64
ADDRESS_WIDTH 32
HAS_READ_BLOCK 1
HAS_WRITE_BLOCK 0
READ_BURSTCOUNT_WIDTH 4
WRITE_BURSTCOUNT_WIDTH 4
BURST_TRANSFER 0
ALWAYS_DO_MAX_BURST 1
DESCRIPTOR_READ_BURST 0
UNALIGNED_TRANSFER 0
CONTROL_SLAVE_DATA_WIDTH 32
CONTROL_SLAVE_ADDRESS_WIDTH 8
DESC_DATA_WIDTH 32
CHAIN_WRITEBACK_DATA_WIDTH 32
STATUS_TOKEN_DATA_WIDTH 24
BYTES_TO_TRANSFER_DATA_WIDTH 16
BURST_DATA_WIDTH 8
CONTROL_DATA_WIDTH 8
ATLANTIC_CHANNEL_DATA_WIDTH 4
COMMAND_FIFO_DATA_WIDTH 104
SYMBOLS_PER_BEAT 8
IN_ERROR_WIDTH 0
OUT_ERROR_WIDTH 0

lcd_ta_sgdma_to_fifo

timing_adapter v9.0
lcd_sgdma out   lcd_ta_sgdma_to_fifo
  in
ddr_sdram sysclk  
  clk
out   lcd_pixel_fifo
  in


Parameters

generationLanguage VERILOG
inBitsPerSymbol 8
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 8
inUseEmpty false
inUseEmptyPort AUTO
inUsePackets true
inUseReady true
inUseValid true
moduleName
outReadyLatency 1
outUseReady true
outUseValid true
  

Software Assignments

(none)

lcd_pixel_fifo

altera_avalon_fifo v9.0
lcd_ta_sgdma_to_fifo out   lcd_pixel_fifo
  in
pll c0  
  clk_out
ddr_sdram sysclk  
  clk_in
out   lcd_ta_fifo_to_dfa
  in


Parameters

avalonMMAvalonMMDataWidth 32
avalonMMAvalonSTDataWidth 32
bitsPerSymbol 8
channelWidth 0
errorWidth 0
fifoDepth 128
fifoInputInterfaceOptions AVALONST_SINK
fifoOutputInterfaceOptions AVALONST_SOURCE
showHiddenFeatures false
singleClockMode false
symbolsPerBeat 8
useBackpressure true
useIRQ false
usePacket true
useReadControl false
useRegister false
useWriteControl false
  

Software Assignments

FIFO_DEPTH 128
AVALONMM_AVALONMM_DATA_WIDTH 32
USE_AVALONMM_WRITE_SLAVE 0
USE_AVALONMM_READ_SLAVE 0
USE_AVALONST_SINK 1
USE_AVALONST_SOURCE 1
USE_REGISTER 0
SINGLE_CLOCK_MODE 0
USE_WRITE_CONTROL 0
USE_READ_CONTROL 0
USE_IRQ 0
USE_BACKPRESSURE 1
BITS_PER_SYMBOL 8
SYMBOLS_PER_BEAT 8
AVALONMM_AVALONST_DATA_WIDTH 32
ERROR_WIDTH 0
CHANNEL_WIDTH 0
USE_PACKET 1

lcd_ta_fifo_to_dfa

timing_adapter v9.0
lcd_pixel_fifo out   lcd_ta_fifo_to_dfa
  in
pll c0  
  clk
out   lcd_64_to_32_bits_dfa
  in


Parameters

generationLanguage VERILOG
inBitsPerSymbol 8
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 1
inSymbolsPerBeat 8
inUseEmpty false
inUseEmptyPort AUTO
inUsePackets true
inUseReady true
inUseValid true
moduleName
outReadyLatency 0
outUseReady true
outUseValid true
  

Software Assignments

(none)

lcd_64_to_32_bits_dfa

data_format_adapter v9.0
lcd_ta_fifo_to_dfa out   lcd_64_to_32_bits_dfa
  in
pll c0  
  clk
out   lcd_pixel_converter
  in


Parameters

generationLanguage VERILOG
inBitsPerSymbol 8
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 8
inUseEmpty false
inUseEmptyPort AUTO
inUsePackets true
inUseReady true
moduleName
outSymbolsPerBeat 4
outUseEmpty false
outUseEmptyPort AUTO
  

Software Assignments

(none)

lcd_pixel_converter

altera_avalon_pixel_converter v9.0
lcd_64_to_32_bits_dfa out   lcd_pixel_converter
  in
pll c0  
  clk
out   lcd_32_to_8_bits_dfa
  in


Parameters

SOURCE_SYMBOLS_PER_BEAT 3
  

Software Assignments

(none)

lcd_32_to_8_bits_dfa

data_format_adapter v9.0
lcd_pixel_converter out   lcd_32_to_8_bits_dfa
  in
pll c0  
  clk
out   lcd_sync_generator
  in


Parameters

generationLanguage VERILOG
inBitsPerSymbol 8
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 3
inUseEmpty false
inUseEmptyPort AUTO
inUsePackets true
inUseReady true
moduleName
outSymbolsPerBeat 1
outUseEmpty true
outUseEmptyPort AUTO
  

Software Assignments

(none)

lcd_sync_generator

altera_avalon_video_sync_generator v9.0
lcd_32_to_8_bits_dfa out   lcd_sync_generator
  in
pll c0  
  clk


Parameters

DATA_STREAM_BIT_WIDTH 8
BEATS_PER_PIXEL 3
NUM_COLUMNS 800
NUM_ROWS 480
H_BLANK_PIXELS 216
H_FRONT_PORCH_PIXELS 40
H_SYNC_PULSE_PIXELS 1
H_SYNC_PULSE_POLARITY 0
V_BLANK_LINES 35
V_FRONT_PORCH_LINES 10
V_SYNC_PULSE_LINES 1
V_SYNC_PULSE_POLARITY 0
TOTAL_HSCAN_PIXELS 1056
TOTAL_VSCAN_LINES 525
  

Software Assignments

(none)

onchip_memory2_0

altera_avalon_onchip_memory2 v9.0
cpu tightly_coupled_instruction_master_0   onchip_memory2_0
  s1
tightly_coupled_data_master_0  
  s2
pll c0  
  clk1
c0  
  clk2


Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
dualPort true
initMemContent true
initializationFileName onchip_memory2_0
instanceID NONE
memorySize 1024
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "onchip_memory2_0"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 1
SIZE_VALUE 1024u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

generation took 0.02 seconds
rendering took 7.91 seconds