| File | Description |
|---|
| ddr_sdram.v | A MegaCore® function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software. |
| ddr_sdram.qip | Contains Quartus II project information for your MegaCore function variation. |
| ddr_sdram.html | The MegaCore function report file. |
| auk_ddr_hp_controller.ocp | An OpenCore Plus file, for time limited or tethered hardware evaluation. |
| auk_ddr_hp_controller.vhd | Encrypted source code for the controller. |
| ddr_sdram_example_driver.v | Example self-checking test generator that matches your variation. |
| ddr_sdram_example_top.v | Example top level design file that you should set as your Quartus II project top level. Instantiates the example driver and the controller. |
| ddr_sdram_example_top.sdc | Example Synopsys Design Constraints file for paths in the example top level. |
| ddr_sdram_advisor.ipa | IP Advisor file that matches your variation. Used by the IP Advisor feature in the Quartus II software. |
| ddr_sdram_ex_lfsr8.v | Example linear feedback shift register that is used to generate the pseudo-random test data for the example driver. |
| testbench | ddr_sdram_example_top_tb.v | Example testbench that instantiates the example top level design file and the example memory model. |
| testbench | ddr_sdram_mem_model.v | A simple example memory model that matches your variation. |
| testbench | ddr_sdram_full_mem_model.v | Memory model that allocates memory for all available addresses. |
| ddr_sdram_pin_assignments.tcl | TCL script |