Generation Report - Triple Speed Ethernet MegaCore Function v7.2

Entity Name	altera_tse_mac
Variation Name	tse_mac
Variation HDL	Verilog HDL
Output Directory	C:\works\Small_MAC_10-100

File Summary

The MegaWizard interface is creating the following files in the output directory:

File	Description
tse_mac.v	A MegaCore^® function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.
tse_mac.vo	Verilog HDL IP functional simulation model
tse_mac.qip	Contains Quartus II project information for your MegaCore function variation.
tse_mac.html	The MegaCore function report file.

MegaCore Function Variation File Ports

Name	Direction	Width
ff_tx_crc_fwd	INPUT	1
ff_tx_data	INPUT	32
ff_tx_eop	INPUT	1
ff_tx_err	INPUT	1
ff_tx_mod	INPUT	2
ff_tx_rdy	OUTPUT	1
ff_tx_sop	INPUT	1
ff_tx_wren	INPUT	1
ff_tx_clk	INPUT	1
ff_rx_data	OUTPUT	32
ff_rx_dval	OUTPUT	1
ff_rx_eop	OUTPUT	1
ff_rx_mod	OUTPUT	2
ff_rx_rdy	INPUT	1
ff_rx_sop	OUTPUT	1
rx_err	OUTPUT	6
rx_err_stat	OUTPUT	18
rx_frm_type	OUTPUT	4
ff_rx_dsav	OUTPUT	1
ff_rx_clk	INPUT	1
address	INPUT	8
readdata	OUTPUT	32
read	INPUT	1
writedata	INPUT	32
write	INPUT	1
waitrequest	OUTPUT	1
clk	INPUT	1
reset	INPUT	1
m_rx_d	INPUT	4
m_rx_en	INPUT	1
m_rx_err	INPUT	1
m_tx_d	OUTPUT	4
m_tx_en	OUTPUT	1
m_tx_err	OUTPUT	1
tx_clk	INPUT	1
rx_clk	INPUT	1
set_10	INPUT	1
set_1000	INPUT	1
ena_10	OUTPUT	1
eth_mode	OUTPUT	1
ff_tx_septy	OUTPUT	1
tx_ff_uflow	OUTPUT	1
ff_rx_a_full	OUTPUT	1
ff_rx_a_empty	OUTPUT	1
ff_tx_a_full	OUTPUT	1
ff_tx_a_empty	OUTPUT	1
mdio_out	OUTPUT	1
mdio_oen	OUTPUT	1
mdio_in	INPUT	1
mdc	OUTPUT	1
m_rx_col	INPUT	1
m_rx_crs	INPUT	1