Arria 10 Transceiver PHY Design Examples

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Contents

Overview

This article lists the specifications and design zip files for Arria 10 Transceiver PHY design examples. The purpose of design examples is to assist the user with Arria 10 transceiver designs by giving a verified and easy to understand stand-alone design example. Each design example zip file has a user guide and necessary design files. The user guide helps to understand design example and provides instructions on how to simulate and compile.The design examples are available for Quartus v13.1a10 and for Quartus v14.0a10. Design examples for Quartus v14.0a10 are not backward compatible with Quartus v13.1a10 because of changes in Quartus Megawizard tool.

PIPE Design Example

PIPE design examples show implementation of Gen1 x4,Gen2 x8,Gen3 x1 and Gen3 x8 PIPE using Native PHY.

PIPE Design File

Arria 10 PIPE Design Example File QII v17.1.1

PIPE SDC Creation Guideline

Arria_10_PIPE_SDC_Creation_Guideline.pdf     

PIPE SDC Example

SDC_Example (ZIP)     

PIPE Design Specifications

The table below lists the specifications for this design:

Attribute Specification
Device Arria 10
Quartus version QuartusII v13.1a10, QuartusII v15.0.0
Modelsim version Modelsim SE v10.1e
Datarate 8Gbps
Data pattern Custom data Pattern
Number of channels 8
IP used Native PHY IP,ATX PLL IP, Transceiver PHY reset controller

Interlaken Design Example

This design example shows implementation of 24channel 12.5G Interlaken design using Native PHY.

Interlaken Design File

Arria 10 Interlaken Design Example File QII v13.1a10(ZIP)     Arria 10 Interlaken Design Example QII v14.0a10(ZIP)

Interlaken Design Specifications

The table below lists the specifications for this design:

Attribute Specification
Device Arria 10
Quartus version QuartusII v13.1a10, QuartusII v14.0a10, QuartusII v15.1a10
Modelsim version Modelsim SE v10.1e
Datarate 12.5Gbps
Data pattern PRBS23 data Pattern
Number of channels 24
IP used Native PHY IP,ATX PLL IP, fPLL IP,Transceiver PHY reset controller

1G/10GbE and 10GBASE-KR PHY Design Example

This design example shows the implementation of 2 channels of 1G/10GbE PHY and 2 channels of 10GBASE-KR PHY IPs.

1G/10GbE and 10GBASE-KR PHY Design File

Arria 10 1G/10G and 10Gbase-KR PHY Design Example File QII v13.1a10(ZIP)    Arria 10 1G/10G and 10Gbase-KR PHY Design Example File QII v14.0a10(ZIP)
Arria 10 1G/10G and 10GBASE-KR PHY Design Example File QII v15.1(ZIP)

1G/10GbE and 10GBASE-KR PHY Design Specifications

The table below lists the specifications for this design:

Attribute Specification
Device Arria 10
Quartus version QuartusII v13.1a10,QuartusII v14.0a10, QuartusII v15.1
Modelsim version Modelsim SE v10.1e
Datarate 10.3125Gbps for 10G and 1.25Gbps for 1G
Data pattern XGMII and GMII pattern generators and checkers
Number of channels 4
IP used 1G/10GbE and 10GBASE-KR PHY IP,ATX PLL IP, CMU PLL IP, FPLL IP, Transceiver PHY reset controller

Transceiver Reconfiguration Design Example using Native PHY

There are two design examples demonstrating the Native PHY IP and PLL IP reconfiguration interfaces. The first design demonstrates how to switch between a 9.8Gbps ATX PLL to a 10.3Gbps ATX PLL. As part of this reconfiguration the channel CDRs are also reconfigured to support the new data rate. The second design demonstrates how to reconfigure a 8.5Gbps to a 10.3Gbps fPLL. As part of this reconfiguration the channel CDRs are also reconfigured to support the new data rate.

Transceiver Reconfiguration Design Files

Transceiver data rate reconfiguration Design Example File QII v13.1a10(ZIP)     Transceiver data rate reconfiguration Design Example File QII v14.0a10(ZIP)
Transceiver pll reconfiguration Design Example File QII v13.1a10(ZIP)     Transceiver pll reconfiguration Design Example File QII v14.0a10(ZIP)

Transceiver Reconfiguration using Native PHY Design Specifications

The table below lists the specifications for this design:

Attribute Specification
Device Arria 10
Quartus version QuartusII v13.1a10,QuartusII v14.0a10
Modelsim version Modelsim SE v10.1e
Datarate Reconfiguration from 9.81Gbps to 10.3125Gbps
Data pattern PRBS31 Data generators and checkers
Number of channels 4
IP used Native PHY IP,ATX PLL IP, Transceiver PHY reset controller


PMA Bonding Design Examples using Native PHY

These design examples shows how to implement Tx skew reduction using six-channel bonded configuration, eighteen-channel bonded configuration. For six-channel bonded configuration x6 PMA bonding is used and for eighteen-channel configuration xN and Pll feedback compensation PMA Bonding are used.

PMA Bonding Design Files

x6 PMA Bonding Design Example File QII v13.1a10 (ZIP)     x6 PMA Bonding Design Example File QII v14.0a10 (ZIP)
xN PMA Bonding Design Example File QII v13.1a10 (ZIP)     xN PMA Bonding Design Example File QII v14.0a10 (ZIP)

pll feedback compensation PMA Bonding Design Example File QII v13.1a10 (ZIP)     pll feedback compensation PMA Bonding Design Example File QII v14.0a10 (ZIP)

Note: ATX PLL feedback compensation mode is not recommended. Consider using xN/x6 bonding.

PMA Bonding using Native PHY Design Specifications

The table below lists the specifications for this design:

Attribute Specification
Device Arria 10
Quartus version QuartusII v13.1a10,QuartusII v14.0a10
Modelsim version Modelsim SE v10.1e
Datarate 10Gbps
Data pattern PRBS Data generators and checkers(Default is PRBS23)
Number of channels 6 channels for x6 bonding and 18 channels for xN and pll feedback compensation bonding
IP used Native PHY IP,ATX PLL IP, Transceiver PHY reset controller





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