CPRI v6 Errata

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Errata List

The following table records the known issues for CPRI v6 IP, full description of each issue is described later in this page. If you need a patch(fix) of this issue in your current build, please contact engineering for support.

Errata no Issued Date Version/Build Description Fix in
376019 11 May, 2016 15.1.313 Ethernet Tx PCS with MII interface may experience packet drop 16.0.249
376021 11 May, 2016 15.1.313 Ethernet Rx PCS with MII interface may experience state machine deadlock 16.0.249
376061 12 May, 2016 15.1.313 Ethernet Tx PCS with GMII interface may experience packet drop 16.1.275
376285 12 May, 2016 15.1.313 Ethernet Tx and Rx PCS with GMII interface could not reset thoroughly 16.1.275
377102 17 May, 2016 15.1.313 Ethernet Tx with MII interface at 3072Mbps may corrupt some packet(s) 16.0.249
380077 30 May, 2016 15.1.313 Stratix V line bit rate auto-negotiation to 9.8304Gbps (or lower rate) may not work 16.0.249
410745 1 Mar, 2017 16.0.249 Incorrect LOS LOF RAI value during reset 16.1.275
436960 1 Mar, 2017 16.0.249 LCV counter has incorrect bit width 16.1.275
440946 1 Mar, 2017 16.1.275 Vendor Specific Slot may be overridden when Pointer-P = 0 16.1.285
440949 1 Mar, 2017 16.1.275 vs_tx_rdy has no assertion or absent on certain basic frame 16.1.285
447072 22 Mar, 2017 16.1.285 SDC error for single-trip delay calibration 17.0.260
475322 7 Aug, 2017 16.1.285 LCV counter causes deadlock in frame re-synchronization 17.0.260
475618 7 Aug, 2017 16.1.285 Register (0x5C) XCVR_BITSLIP - tx_bitslip_en is not connected to transmitter 17.0.260
464675 7 Aug, 2017 16.1.285 Ethernet MII (<3Gbps) has low throughput 17.0.260
447177 7 Aug, 2017 16.1.285 Register (0x30/34/38) CTRL_INDEX/TX_CTRL/RX_CTRL hang during read operation 17.0.260
443827 7 Aug, 2017 16.1.285 Double assertion on aux_tx_rfp_sync may cause link fail 17.0.260
479150 7 Aug, 2017 16.1.285 HDLC serial interface bandwidth issue at 240kbit/s (001) 17.0.260
478490 7 Aug, 2017 16.1.285 Register (0xC) BIT_RATE_CONFIG not in Read-only mode 17.0.260
480483 7 Aug, 2017 16.1.285 aux_tx_err port give false assertion when IF_LATENCY > 0 mode is used 17.0.260
477813 7 Aug, 2017 16.1.285 (Simulation) Link issue in line bit rate option 7A/8 when rate auto-negotiation is turned on 17.0.260
472785 7 Aug, 2017 16.1.285 (Enhancement) Improve soft FIFO initial delay consistency after re-synchronization 17.0.260
435635 7 Aug, 2017 16.1.285 (Enhancement) Additional LOS/LOF bits added in register (0x2C) LFSAR 17.0.260
475609 7 Aug, 2017 16.1.285 Disable Tx local clock division factor (2,4,8) for <5Gbps in Arria 10 17.0.260
475622 7 Aug, 2017 16.1.285 Disable Rx recovered clock option for Arria 10 17.0.260
484198 16 Aug, 2017 17.0.260 "VCCR_GXB and VCCT_GXB supply voltage for the Transceiver" Option is redundant in CPRI GUI TBD
487898 25 Aug, 2017 17.0.260 Line bit rate auto-negotiation should be disabled for 1.2288Gbps in Arria 10/Stratix 10 TBD
507451 1 Nov, 2017 17.0.260 Testbench generation failure in Windows Platform TBD


Fixed in 16.0.249

376019 Ethernet Tx PCS with MII interface may experience packet drop

  • Description  : When sending Jumbo packet(s), Tx Ethernet PCS may drop the packet when Pointer-P is set to minimum (63)
  • Affected configuration : Line bit rate 9.8304Gbps and above
  • Workaround  : No workaround

376021 Ethernet Rx PCS with MII interface may experience state machine deadlock

  • Description  : When Rx Ethernet PCS hit FIFO full condition, the Rx state machine may be stuck and stop processing packet(s)
  • Affected configuration : All configuration with Ethernet PCS MII interface
  • Workaround  : Perform a reset on the Ethernet Rx PCS through mii_rxreset port

377102 Ethernet Tx with MII interface at 3072Mbps may corrupt some packet(s)

  • Description  : Packet(s) may be corrupted when Ethernet Tx PCS is sending multiple packet(s) at 3072Mbps
  • Affected configuration : 3072Mbps
  • Workaround  : Reset Ethernet Tx PCS with mii_txreset

380077 Stratix V line bit rate auto-negotiation to 9.8304Gbps (or lower rate) may not work

  • Description  : Link will be down after switching from 10.1376Gbps to lower rates (8b10b variant)
  • Affected configuration : Stratix V 10.1376 Gbps
  • Workaround  : No workaround (quick RTL fix available for 15.1)


Fixed in 16.1.275

376061 Ethernet Tx PCS with GMII interface may experience packet drop

  • Description  : Tx Ethernet PCS may drop the packet when FIFO almost full or full condition is seen on eth_gmii_tx_fifo port
  • Affected configuration : All configurations
  • Workaround  : No workaround

376285 Ethernet Tx and Rx PCS with GMII interface could not reset thoroughly

  • Description  : Packet(s) may be corrupted when Ethernet PCS is reset with gmii_txreset/gmii_rxreset only without global reset
  • Affected configuration : All configurations
  • Workaround  : Reset both gmii_txreset/gmii_rxreset and global reset/reset_tx/reset_rx

410745 Incorrect LOS LOF RAI value during reset

  • Description  : Local LOS/LOF/RAI bits are not set at 1 during reset stage, receiving partner node may not get correct link information
  • Affected  : All configuration
  • Workaround  : No workaround

436960 LCV counter has incorrect bit width

  • Description  : Line Code Violation (LCV) counter saturated at 4bit and not able to count 16 or more LCV in a hyperframe
  • Affected  : All configuration
  • Workaround  : No workaround


Fixed in 16.1.285

440946 Vendor Specific Slot may be overridden when Pointer-P = 0

  • Description  : When Pointer-P is set to 0, some slot of Vendor Specific (VS) will be override with Ethernet default value 8'hFF
  • Affected  : All configuration
  • Workaround  : No workaround (quick RTL fix available for 16.1.275)

440949 vs_tx_rdy has no assertion or absent on certain basic frame

  • Description  : vs_tx_rdy will not be asserted when Pointer-P is set to 0, and absent in some basic frames (32-47, 96-111, 160-175, 223-239) when Pointer-P value is set to 20-63
  • Affected  : Configuration with Vendor Specific (VS) direct interface enabled
  • Workaround  : No workaround (quick RTL fix available for 16.1.275)


Fixed in 17.0.260

447072 SDC script error for configuration with Single-trip delay calibration enabled

  • Description  : Typo error in generated SDC file which prevent full compilation, halt at fitter stage
  • Affected  : Slave configuration with Single-trip delay calibration feature enabled
  • Workaround  : Edit SDC on line with keyword of "set_Registers" and change to "set_registers"

475322 LCV counter causes deadlock in frame re-synchronization

  • Description  : During CPRI startup, when excessive 8b10b violation is detected, LCV counter not able to reset due to no incoming HFP
  • Affected  : All configuration
  • Workaround  : (hardware) Perform multiple resets when link not able to achieve link synchronization

475618 Register (0x5C) XCVR_BITSLIP - tx_bitslip_en is not connected to transmitter

  • Description  : tx_bitslip_en malfunction as Tx bitslip function is disabled due to port not connected
  • Affected  : All configuration
  • Workaround  : Edit generated wrapper - Connect altera_cpri xcvr_tx_std_bitslipboundaryselect to transceiver tx_std_bitslipboundselect port manually

464675 Ethernet MII (<3Gbps) has low throughput

  • Description  : MII may experience extremely low throughput (<1Mbps) and packet loss conditions
  • Affected  : Ethernet MII configuration with line bit rate 3Gbps and below
  • Workaround  : No workaround (quick fix file for pre-17.0 available)

447177 Register (0x30/34/38) CTRL_INDEX/TX_CTRL/RX_CTRL hang during read operation

  • Description  : Management interface hang (cpu_waitrequest never deassert) when these registers are accessed without "Enable all Control word access via Management interface"
  • Affected  : All configuration without "Enable all Control word access via Management interface"
  • Workaround  : No workaround

443827 Double assertion on aux_tx_rfp_sync may cause link fail

  • Description  : Asserting aux_tx_rfp_sync pulses that is too close (< IF_LATENCY+1) to each other will disrupt the framing process and core may not be able to recover
  • Affected  : All configuration with Auxiliary interface turned on
  • Workaround  : No workaround (quick fix for pre-17.0 available)

479150 HDLC serial interface bandwidth issue at 240kbit/s (001)

  • Description  : Additional hdlc_tx_rdy pulses maybe observed on the HDLC serial interface as bandwidth control is missing in the RTL, HDLC slot(s) are not transmitted/received correctly
  • Affected  : HDLC configuration with Z.66.0 set to 3'b001
  • Workaround  : No workaround

478490 Register (0xC) BIT_RATE_CONFIG not in Read-only mode

  • Description  : Reading register BIT_RATE_CONFIG may return non-static bit rate value
  • Affected  : Configuration with rate auto-negotiation turned off
  • Workaround  : No workaround

480483 aux_tx_err port give false assertion when IF_LATENCY > 0 mode is used

  • Description  : aux_tx_err may asserts incorrectly when IQ slot is written from AUX interface,
  • Affected  : All configuration with Auxiliary interface enabled and interface latency is set to >0
  • Workaround  : No workaround

477813 Link issue in line bit rate option 7A/8 when rate auto-negotiation is turned on

  • Description  : Link may not be able to achieve Hyperframe synchronization in option 7A and 8 due to malfunction in simulation model
  • Affected  : Rate auto-negotiation is turned on for line bit rate option 7A and 8, simulation only
  • Workaround  : No workaround

472785 Improve soft FIFO initial delay consistency after re-synchronization

  • Description  : Upon different reset, additional delay of 5 clock cycles may be observed in soft FIFO
  • Affected  : All configuration
  • Workaround  : Reset core

475609 Removal of Tx local clock division factor value (2,4,8) for lower line bit rate (<5Gbps) Arria 10

  • Description  : These values are not valid and are removed from Arria 10 support to align with NativePHY transceiver
  • Affected  : Arria 10 with line bit rate lower than 5Gbps
  • Workaround  : No workaround

475622 Removal of Rx recovered clock source option for Arria 10

  • Description  : Recovered clock source will be from PCS directly, no other option available
  • Affected  : Arria 10 slave configuration
  • Workaround  : No workaround


Fixed in future releases

484198 "VCCR_GXB and VCCT_GXB supply voltage for the Transceiver" Option is redundant in CPRI GUI when non Stratix 10 devices are selected

  • Description: The option is visible when non Stratix 10 devices are selected but will have no effect
  • Affected: All configurations which uses a non Stratix 10 device
  • Workaround: No workaround - please ignore this parameter option

487898 Line bit rate auto-negotiation should be disabled for 1.2288Gbps in Arria 10

  • Description  : The line bit rate auto-negotiation option in GUI for 1.2288Gbps configuration in Arria 10 is not valid and should be disabled
  • Affected  : All Arria 10 configuration
  • Workaround  : No workaround (please do not enable line bit rate auto-negotiation for Arria 10 1.2288Gbps configuration)

507451 Testbench generation failure in Windows platform

  • Description  : Generation of the IP core simulation files will fail, generation of HDL synthesis files are not affected
  • Affected  : All configuration/device when Windows installer is used
  • Workaround  : Locate the altera_cpri_demo_tb_sim.tcl model file in <quartus installation>/ip/altera_cloud/cpri_ii/altera_cpri_ii_ed/ip_sim/ and change the line of "set dir $::env(PWD)" to "set dir env(%cd%)"
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