Cyclone10 Transceiver PHY Basic Design Examples
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Cyclone10 Transceiver PHY Basic Design Examples
Overview
Cyclone 10 GX Native PHY ATX PLL switching, channel reconfiguration with embedded streamer and channel recalibration design example
This basic design example with Modelsim simulation demonstrates the implementation of Cyclone 10 GX Native PHY ATX PLL switching, channel reconfiguration with embedded streamer as well as channel recalibration. The two ATX PLLs are used to support two different data rates which could not be achieved with TX local divider. The purpose of this design example is to assist users to have quick start with the Cyclone 10 GX transceiver dynamic reconfiguration with embedded streamer and multiple profiles. The simulation start with XCVR running at 2Gbps data rate and then reconfigure to 1.5Gbps using ATX PLL switching and channel reconfiguration. After reconfiguration is completed, a channel recalibration followed by reset is performed.
The design also comes with example test bench and TCL files to run simulation in Modelsim for reference. Note that you should create your reconfiguration controller and AVMM read/write controller as these controls are done in test bench in the example. The register values to write for ATX PLL switching and channel recalibration here were obtained by manually reading from simulation and modify. You should create your own mechanism to perform on-the-fly read-modify-write for ATX PLL switching and channel recalibration.
To run the simulation, do the following:
1. Unzip the files
2. Change the Modelsim directory to the "\simulation\mentor" folder
3. Type "source msim_setup.tcl"
4. Type "ld" to compile
5. Type "simulate" to start simulation
Design File
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Cyclone 10 GX |
| Quartus version | Quartus Prime v17.1 Pro Edition |
| Modelsim version | ModelSim - Intel FPGA Edition 10.5c |
| Datarate | 2Gbps and 1.5Gbps |
| Data pattern | Fixed |
| Number of channels | 1 |
| IP used | Native PHY IP, ATX PLL, Transceiver PHY Reset Controller |
Cyclone 10 GX Native PHY fPLL switching and channel reconfiguration with direct write method design example
Overview
This basic design example with Modelsim simulation demonstrates the implementation of Cyclone 10 GX Native PHY fPLL switching and channel reconfiguration using direct write method. The two fPLLs are used to support two different data rates which could not be achieved with TX local divider. The purpose of this design example is to assist users to have quick start with the Cyclone 10 GX transceiver dynamic reconfiguration using direct write method. The simulation start with XCVR running at 2Gbps data rate and then reconfigures to 1.5Gbps using fPLL switching and channel reconfiguration. After reconfiguration is completed, a channel recalibration is performed.
The design also comes with example test bench and TCL files to run simulation in Modelsim for reference. Note that you should create your reconfiguration controller and AVMM read/write controller as these controls are done in test bench in the example. The register values to write for fPLL switching and channel recalibration here were obtained by manually reading from simulation and modify. The register address to change for Native PHY reconfiguration is determined by comparing the <>_CFG0.v and <>_CFG1.v files at native_tx0\altera_xcvr_native_a10_171\sim\reconfig. The register values to write were obtained by manually reading from simulation and modify. You should create your own mechanism to perform on-the-fly read-modify-write for fPLL switching, channel reconfiguration and channel recalibration.
To run the simulation, do the following:
1. Unzip the files
2. Change the Modelsim directory to the "\simulation\mentor" folder
3. Type "source msim_setup.tcl"
4. Type "ld" to compile
5. Type "simulate" to start simulation
Design File
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Cyclone 10 GX |
| Quartus version | Quartus Prime v17.1 Pro Edition |
| Modelsim version | ModelSim - Intel FPGA Edition 10.5c |
| Datarate | 2Gbps and 1.5Gbps |
| Data pattern | Fixed |
| Number of channels | 1 |
| IP used | Native PHY IP, fPLL, Transceiver PHY Reset Controller |
Cyclone 10 GX Native PHY ATX PLL reference clock switching, ATX PLL and channel reconfiguration with embedded streamer and recalibration design example
Overview
This basic design example with Modelsim simulation demonstrates the implementation of Cyclone 10 GX ATX PLL refclk switching, ATX PLL reconfiguration with embedded streamer, channel reconfiguration with embedded streamer, ATX PLL and channel recalibration. A single ATX PLL is used to support two different data rates which could not be achieved with TX local divider. Therefore, we would require ATX PLL refclk switching and reconfiguration to switch between these two data rates. The purpose of this design example is to assist users to have quick start with the Cyclone 10 GX transceiver dynamic reconfiguration with ATX PLL refclk switching. The simulation start with XCVR running at 2Gbps data rate and then reconfigure to 1.2Gbps using ATX PLL refclk switching reconfiguration. After reconfiguration is completed, ATX PLL and channel recalibration followed by reset is performed.
The design also comes with example test bench and TCL files to run simulation in Modelsim for reference. Note that you should create your reconfiguration controller and AVMM read/write controller as these controls are done in test bench in the example.
To run the simulation, do the following:
1. Unzip the files
2. Change the Modelsim directory to the "\simulation1\mentor" folder
3. Type "source msim_setup.tcl"
4. Type "ld" to compile
5. Type "simulate" to start simulation
Design File
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Cyclone 10 GX |
| Quartus version | Quartus Prime v17.1 Pro Edition |
| Modelsim version | ModelSim - Intel FPGA Edition 10.5c |
| Datarate | 2Gbps and 1.2Gbps |
| Data pattern | Fixed |
| Number of channels | 1 |
| IP used | Native PHY IP, ATX PLL, Transceiver PHY Reset Controller |
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