FTA Low latency 10G MAC Data Corruption Issue

From Intel FPGA Wiki
Jump to: navigation, search

Contents

Last Major Update

JUNE 17, 2015

 

Introduction

Fault Tree Analysis (FTA) uses tree structures to decompose system level failures into combinations of lower-level events, and Boolean gates to model their interactions. The objective of this debug FTA example is to help troubleshoot and identify issue related to Altera Low Latency Ethernet 10G MAC Megacore and resolve it effectively.

Data corruption failure in Ethernet System is a very common issue that user might encounter. The complexity of such issue's debugging are due to below factors:

i) Multiple possible root causes
ii) Difficult to isolate the problem to a specific area of the design.
iii) Requires significant effort and time to isolate the hypothesis.


Fault Tree Analysis Diagram & Table

The FTA example : FTA_LL_10G_MAC_Data_Corruption_issue consists of a FTA diagram and table used to debug and root cause the data corruption failure issue happens in the Low Latency 10G MAC Ethernet system. In the FTA diagram, multiple hypothesis are make based on the failure symptom as described. For each of the hypothesis, it can have 2nd level or up to 3rd level suspects. The FTA diagram will then be converted into a table format to proper keep track of the debug progress. In the FTA table, for every suspect listed , it needs to have some action items to be performed to verify it together with some additional category information to be filled in such as Owner, Target completion date, status/Results, Possible Next Step and Priority level.

Disclaimer

© [2013] Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate.

Personal tools