SYSTEM NiosII_stratix_1s40_full_featured
{
System_Wizard_Version = "7.20";
System_Wizard_Build = "150";
Builder_Application = "sopc_builder_ca";
WIZARD_SCRIPT_ARGUMENTS
{
hdl_language = "verilog";
device_family = "STRATIX";
device_family_id = "STRATIX";
generate_sdk = "0";
do_build_sim = "1";
hardcopy_compatible = "0";
CLOCKS
{
CLOCK clk
{
frequency = "50000000";
source = "External";
Is_Clock_Source = "0";
display_name = "clk";
pipeline = "0";
clock_module_connection_point_for_c2h = "clk.clk";
}
CLOCK pll_c0
{
frequency = "50000000";
source = "";
Is_Clock_Source = "1";
display_name = "c0 from pll";
pipeline = "0";
clock_module_connection_point_for_c2h = "pll.c0";
}
CLOCK pll_c0_out
{
frequency = "50000000";
source = "pll_c0";
Is_Clock_Source = "0";
display_name = "pll_c0_out";
}
CLOCK pll_e0
{
frequency = "50000000";
source = "";
Is_Clock_Source = "1";
display_name = "e0 from pll";
pipeline = "0";
clock_module_connection_point_for_c2h = "pll.e0";
}
CLOCK pll_e0_out
{
frequency = "50000000";
source = "pll_e0";
Is_Clock_Source = "0";
display_name = "pll_e0_out";
}
}
clock_freq = "50000000";
clock_freq = "50000000";
board_class = "";
view_master_columns = "1";
view_master_priorities = "0";
generate_hdl = "";
bustype_column_width = "0";
clock_column_width = "80";
name_column_width = "75";
desc_column_width = "75";
base_column_width = "75";
end_column_width = "75";
BOARD_INFO
{
altera_avalon_cfi_flash
{
reference_designators = "";
}
}
do_log_history = "0";
}
MODULE pll
{
SLAVE s1
{
PORT_WIRING
{
PORT inclk0
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT resetrequest
{
type = "resetrequest";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "3";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT read
{
type = "read";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT readdata
{
type = "readdata";
width = "16";
direction = "output";
Is_Enabled = "1";
}
PORT write
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "16";
direction = "input";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT c0
{
Is_Enabled = "1";
direction = "output";
type = "out_clk";
width = "1";
}
PORT e0
{
Is_Enabled = "1";
direction = "output";
type = "out_clk";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "16";
Address_Width = "3";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x00800020";
}
Clock_Source = "clk";
Has_Clock = "1";
Base_Address = "0x00800020";
Has_IRQ = "0";
Date_Modified = "";
Instantiate_In_System_Module = "1";
Requires_Internal_Clock_Promotion = "Yes";
Is_Clock_Source = "1";
Address_Group = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
PORT_WIRING
{
PORT c0
{
type = "out_clk";
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT e0
{
type = "out_clk";
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT areset
{
Is_Enabled = "0";
direction = "input";
width = "1";
}
PORT locked
{
Is_Enabled = "0";
direction = "output";
width = "1";
}
PORT pfdena
{
Is_Enabled = "0";
direction = "input";
width = "1";
}
PORT pllena
{
Is_Enabled = "0";
direction = "input";
width = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
areset = "None";
pfdena = "None";
locked = "None";
pllena = "None";
scanclk = "None";
scandata = "None";
scanread = "None";
scanwrite = "None";
scanclkena = "None";
scanaclr = "None";
scandataout = "None";
scandone = "None";
configupdate = "None";
phasecounterselect = "None";
phasedone = "None";
phaseupdown = "None";
phasestep = "None";
UI_CONTROL
{
pllena_port_exist = "0";
areset_port_exist = "0";
pfdena_port_exist = "0";
locked_port_exist = "0";
}
ALTPLL_PORTS
{
PORT inclk0
{
Is_Enabled = "1";
direction = "input";
width = "1";
}
PORT c0
{
Is_Enabled = "1";
direction = "output";
type = "out_clk";
width = "1";
}
PORT e0
{
Is_Enabled = "1";
direction = "output";
type = "out_clk";
width = "1";
}
}
CLOCK_SOURCES
{
CLOCK c0
{
DIVIDE_BY = "1";
DUTY_CYCLE = "50";
MULTIPLY_BY = "1";
PHASE_SHIFT = "0";
clk_index = "0";
clock_freq = "50000000";
clock_unit = "MHz";
type = "out_clk";
}
CLOCK e0
{
DIVIDE_BY = "1";
DUTY_CYCLE = "50";
MULTIPLY_BY = "1";
PHASE_SHIFT = "-3500";
clk_index = "6";
clock_freq = "50000000";
clock_unit = "MHz";
type = "out_clk";
}
}
CLOCK_INFO
{
CLOCK inclk0
{
clock_freq = "50000000";
clock_unit = "MHz";
type = "in_clk";
}
}
CNX_INFO
{
CONSTANT
{
STRING
{
BANDWIDTH_TYPE = "AUTO";
COMPENSATE_CLOCK = "CLK0";
INTENDED_DEVICE_FAMILY = "STRATIX";
LPM_TYPE = "altpll";
OPERATION_MODE = "NORMAL";
PLL_TYPE = "AUTO";
PORT_ACTIVECLOCK = "PORT_UNUSED";
PORT_ARESET = "PORT_UNUSED";
PORT_CLKBAD0 = "PORT_UNUSED";
PORT_CLKBAD1 = "PORT_UNUSED";
PORT_CLKLOSS = "PORT_UNUSED";
PORT_CLKSWITCH = "PORT_UNUSED";
PORT_FBIN = "PORT_UNUSED";
PORT_INCLK0 = "PORT_USED";
PORT_INCLK1 = "PORT_UNUSED";
PORT_LOCKED = "PORT_UNUSED";
PORT_PFDENA = "PORT_UNUSED";
PORT_PLLENA = "PORT_UNUSED";
PORT_SCANACLR = "PORT_UNUSED";
PORT_SCANCLK = "PORT_UNUSED";
PORT_SCANDATA = "PORT_UNUSED";
PORT_SCANDATAOUT = "PORT_UNUSED";
PORT_SCANDONE = "PORT_UNUSED";
PORT_SCANREAD = "PORT_UNUSED";
PORT_SCANWRITE = "PORT_UNUSED";
PORT_clk0 = "PORT_USED";
PORT_clk1 = "PORT_UNUSED";
PORT_clk2 = "PORT_UNUSED";
PORT_clk3 = "PORT_UNUSED";
PORT_clk4 = "PORT_UNUSED";
PORT_clk5 = "PORT_UNUSED";
PORT_clkena0 = "PORT_UNUSED";
PORT_clkena1 = "PORT_UNUSED";
PORT_clkena2 = "PORT_UNUSED";
PORT_clkena3 = "PORT_UNUSED";
PORT_clkena4 = "PORT_UNUSED";
PORT_clkena5 = "PORT_UNUSED";
PORT_enable0 = "PORT_UNUSED";
PORT_enable1 = "PORT_UNUSED";
PORT_extclk0 = "PORT_USED";
PORT_extclk1 = "PORT_UNUSED";
PORT_extclk2 = "PORT_UNUSED";
PORT_extclk3 = "PORT_UNUSED";
PORT_extclkena0 = "PORT_UNUSED";
PORT_extclkena1 = "PORT_UNUSED";
PORT_extclkena2 = "PORT_UNUSED";
PORT_extclkena3 = "PORT_UNUSED";
PORT_sclkout0 = "PORT_UNUSED";
PORT_sclkout1 = "PORT_UNUSED";
}
NUMERIC
{
INCLK0_INPUT_FREQUENCY = "20000";
INVALID_LOCK_MULTIPLIER = "5";
SPREAD_FREQUENCY = "0";
VALID_LOCK_MULTIPLIER = "1";
CLK0_MULTIPLY_BY = "1";
CLK0_DIVIDE_BY = "1";
CLK0_PHASE_SHIFT = "0.0";
EXTCLK0_MULTIPLY_BY = "1";
EXTCLK0_DIVIDE_BY = "1";
EXTCLK0_PHASE_SHIFT = "-3500.0";
}
}
GEN_FILE
{
TYPE_NORMAL
{
TRUE
{
File1 = ".v";
File2 = ".ppf";
}
FALSE
{
File3 = ".inc";
File4 = ".cmp";
File5 = ".bsf";
File6 = "_inst.v";
File7 = "_bb.v";
File8 = "_waveforms.html";
File9 = "_wave*.jpg";
}
}
}
LIBRARY = "altera_mf altera_mf.altera_mf_components.all";
PRIVATE
{
STRING
{
ACTIVECLK_CHECK = "0";
BANDWIDTH = "1.000";
BANDWIDTH_FEATURE_ENABLED = "1";
BANDWIDTH_FREQ_UNIT = "MHz";
BANDWIDTH_PRESET = "Low";
BANDWIDTH_USE_AUTO = "1";
BANDWIDTH_USE_CUSTOM = "0";
BANDWIDTH_USE_PRESET = "0";
CLKBAD_SWITCHOVER_CHECK = "0";
CLKLOSS_CHECK = "0";
CLKSWITCH_CHECK = "0";
CNX_NO_COMPENSATE_RADIO = "0";
CREATE_CLKBAD_CHECK = "0";
CREATE_INCLK1_CHECK = "0";
CUR_DEDICATED_CLK = "c0";
CUR_FBIN_CLK = "e0";
DEVICE_SPEED_GRADE = "Any";
EXT_FEEDBACK_RADIO = "0";
GLOCKED_COUNTER_EDIT_CHANGED = "1";
GLOCKED_FEATURE_ENABLED = "0";
GLOCKED_MODE_CHECK = "0";
HAS_MANUAL_SWITCHOVER = "1";
INCLK0_FREQ_EDIT = "50.0";
INCLK0_FREQ_UNIT_COMBO = "MHz";
INCLK1_FREQ_EDIT = "100.000";
INCLK1_FREQ_EDIT_CHANGED = "1";
INCLK1_FREQ_UNIT_CHANGED = "1";
INCLK1_FREQ_UNIT_COMBO = "MHz";
INTENDED_DEVICE_FAMILY = "Stratix";
INT_FEEDBACK__MODE_RADIO = "1";
LOCKED_OUTPUT_CHECK = "0";
LOCK_LOSS_SWITCHOVER_CHECK = "0";
LONG_SCAN_RADIO = "1";
LVDS_MODE_DATA_RATE = "Not Available";
NORMAL_MODE_RADIO = "1";
PLL_ADVANCED_PARAM_CHECK = "0";
PLL_ARESET_CHECK = "0";
PLL_ENA_CHECK = "0";
PLL_PFDENA_CHECK = "0";
PRIMARY_CLK_COMBO = "inclk0";
SACN_INPUTS_CHECK = "0";
SCAN_FEATURE_ENABLED = "1";
SELF_RESET_LOCK_LOSS = "0";
SHORT_SCAN_RADIO = "0";
SPREAD_FEATURE_ENABLED = "1";
SPREAD_FREQ = "50.000";
SPREAD_FREQ_UNIT = "KHz";
SPREAD_PERCENT = "0.500";
SPREAD_USE = "0";
SRC_SYNCH_COMP_RADIO = "0";
SWITCHOVER_FEATURE_ENABLED = "1";
ZERO_DELAY_RADIO = "0";
}
NUMERIC
{
DEVICE_FAMILY = "9";
GLOCK_COUNTER_EDIT = "1048575";
LVDS_MODE_DATA_RATE_DIRTY = "0";
PLL_AUTOPLL_CHECK = "1";
PLL_ENHPLL_CHECK = "0";
PLL_FASTPLL_CHECK = "0";
PLL_LVDS_PLL_CHECK = "0";
PLL_TARGET_HARCOPY_CHECK = "0";
SWITCHOVER_COUNT_EDIT = "1";
}
}
USED_PORT
{
inclk0
{
VALUE_1 = "0";
VALUE_2 = "0";
VALUE_3 = "0";
VALUE_4 = "0";
VALUE_5 = "INPUT_CLK_EXT";
VALUE_6 = "GND";
VALUE_7 = "inclk0";
}
c0
{
VALUE_1 = "0";
VALUE_2 = "0";
VALUE_3 = "0";
VALUE_4 = "0";
VALUE_5 = "OUTPUT_CLK_EXT";
VALUE_6 = "VCC";
VALUE_7 = "c0";
}
e0
{
VALUE_1 = "0";
VALUE_2 = "0";
VALUE_3 = "0";
VALUE_4 = "0";
VALUE_5 = "OUTPUT_CLK_EXT";
VALUE_6 = "VCC";
VALUE_7 = "e0";
}
}
}
Config_Done = "0";
}
SYSTEM_BUILDER_INFO
{
Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIII,STRATIXIIGX,CYCLONE,CYCLONEII,CYCLONEIII,ARRIAGX,STRATIXIIGXLITE";
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "pll";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
MESSAGES
{
}
Settings_Summary = " Avalon PLL:
input clock configured: clk
";
}
}
class = "altera_avalon_pll";
class_version = "7.07";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/pll.v, __PROJECT_DIRECTORY__/altpllpll.v";
Synthesis_Only_Files = "";
}
}
MODULE cpu
{
MASTER instruction_master
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT i_address
{
type = "address";
width = "26";
direction = "output";
Is_Enabled = "1";
}
PORT i_read
{
type = "read";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT i_readdata
{
type = "readdata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT i_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT i_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "0";
Do_Stream_Writes = "0";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "28";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "";
Linewrap_Bursts = "";
Burst_On_Burst_Boundaries_Only = "";
Always_Burst_Max_Burst = "";
Is_Big_Endian = "0";
Is_Enabled = "1";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Address_Group = "0";
Has_IRQ = "0";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-0";
}
MEMORY_MAP
{
Entry cpu/jtag_debug_module
{
address = "0x02120000";
span = "0x00000800";
}
Entry ext_flash/s1
{
address = "0x00000000";
span = "0x00800000";
}
Entry ext_ram/s1
{
address = "0x02000000";
span = "0x00100000";
}
Entry lan91c111/s1
{
address = "0x02110000";
span = "0x00010000";
}
Entry onchip_ram/s1
{
address = "0x02100000";
span = "0x00010000";
}
Entry sdram/s1
{
address = "0x01000000";
span = "0x01000000";
}
}
}
MASTER custom_instruction_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "nios_custom_instruction";
Data_Width = "32";
Address_Width = "8";
Is_Custom_Instruction = "1";
Is_Enabled = "1";
Max_Address_Width = "8";
Base_Address = "N/A";
Is_Visible = "0";
}
PORT_WIRING
{
PORT dataa
{
type = "dataa";
width = "32";
direction = "output";
Is_Enabled = "0";
}
PORT datab
{
type = "datab";
width = "32";
direction = "output";
Is_Enabled = "0";
}
PORT result
{
type = "result";
width = "32";
direction = "input";
Is_Enabled = "0";
}
PORT clk_en
{
type = "clk_en";
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT reset
{
type = "reset";
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT start
{
type = "start";
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT done
{
type = "done";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT n
{
type = "n";
width = "8";
direction = "output";
Is_Enabled = "0";
}
PORT a
{
type = "a";
width = "5";
direction = "output";
Is_Enabled = "0";
}
PORT b
{
type = "b";
width = "5";
direction = "output";
Is_Enabled = "0";
}
PORT c
{
type = "c";
width = "5";
direction = "output";
Is_Enabled = "0";
}
PORT readra
{
type = "readra";
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT readrb
{
type = "readrb";
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT writerc
{
type = "writerc";
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT E_ci_combo_a
{
Is_Enabled = "1";
direction = "output";
type = "combo_a";
width = "5";
}
PORT E_ci_combo_b
{
Is_Enabled = "1";
direction = "output";
type = "combo_b";
width = "5";
}
PORT E_ci_combo_c
{
Is_Enabled = "1";
direction = "output";
type = "combo_c";
width = "5";
}
PORT E_ci_combo_dataa
{
Is_Enabled = "1";
direction = "output";
type = "combo_dataa";
width = "32";
}
PORT E_ci_combo_datab
{
Is_Enabled = "1";
direction = "output";
type = "combo_datab";
width = "32";
}
PORT E_ci_combo_estatus
{
Is_Enabled = "1";
direction = "output";
type = "combo_estatus";
width = "1";
}
PORT E_ci_combo_ipending
{
Is_Enabled = "1";
direction = "output";
type = "combo_ipending";
width = "32";
}
PORT E_ci_combo_n
{
Is_Enabled = "1";
direction = "output";
type = "combo_n";
width = "8";
}
PORT E_ci_combo_readra
{
Is_Enabled = "1";
direction = "output";
type = "combo_readra";
width = "1";
}
PORT E_ci_combo_readrb
{
Is_Enabled = "1";
direction = "output";
type = "combo_readrb";
width = "1";
}
PORT E_ci_combo_result
{
Is_Enabled = "1";
direction = "input";
type = "combo_result";
width = "32";
}
PORT E_ci_combo_status
{
Is_Enabled = "1";
direction = "output";
type = "combo_status";
width = "1";
}
PORT E_ci_combo_writerc
{
Is_Enabled = "1";
direction = "output";
type = "combo_writerc";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
}
}
SLAVE jtag_debug_module
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "2048";
Read_Latency = "0";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "32";
Address_Width = "9";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Accepts_External_Connections = "1";
Requires_Internal_Connections = "";
MASTERED_BY cpu/instruction_master
{
priority = "1";
Offset_Address = "0x02120000";
}
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x02120000";
}
Base_Address = "0x02120000";
Is_Readable = "1";
Is_Writeable = "1";
Uses_Tri_State_Data_Bus = "0";
Has_IRQ = "0";
JTAG_Hub_Base_Id = "1118278";
JTAG_Hub_Instance_Id = "0";
Address_Group = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
PORT_WIRING
{
PORT jtag_debug_module_address
{
type = "address";
width = "9";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_begintransfer
{
type = "begintransfer";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_byteenable
{
type = "byteenable";
width = "4";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_debugaccess
{
type = "debugaccess";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT jtag_debug_module_reset
{
type = "reset";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_resetrequest
{
type = "resetrequest";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT jtag_debug_module_select
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_write
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
}
}
MASTER tightly_coupled_data_master_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "0";
Do_Stream_Writes = "0";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "28";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
PORT_WIRING
{
PORT dcm0_address
{
type = "address";
width = "28";
direction = "output";
Is_Enabled = "1";
}
PORT dcm0_byteenable
{
type = "byteenable";
width = "4";
direction = "output";
Is_Enabled = "1";
}
PORT dcm0_clken
{
type = "clken";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT dcm0_read
{
type = "read";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT dcm0_readdata
{
type = "readdata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT dcm0_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT dcm0_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT dcm0_write
{
type = "write";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT dcm0_writedata
{
type = "writedata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
}
MEMORY_MAP
{
Entry tightly_coupled_data_memory/s1
{
address = "0x08002000";
span = "0x00002000";
}
}
}
MASTER data_master
{
SYSTEM_BUILDER_INFO
{
Has_IRQ = "1";
Irq_Scheme = "individual_requests";
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "0";
Do_Stream_Writes = "0";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "28";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Is_Data_Master = "1";
Address_Group = "0";
Is_Readable = "1";
Is_Writeable = "1";
Interrupt_Range = "0-31";
}
PORT_WIRING
{
PORT d_irq
{
type = "irq";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT d_address
{
type = "address";
width = "28";
direction = "output";
Is_Enabled = "1";
}
PORT d_byteenable
{
type = "byteenable";
width = "4";
direction = "output";
Is_Enabled = "1";
}
PORT d_read
{
type = "read";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT d_readdata
{
type = "readdata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT d_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT d_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT d_write
{
type = "write";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT d_writedata
{
type = "writedata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT jtag_debug_module_debugaccess_to_roms
{
type = "debugaccess";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
MEMORY_MAP
{
Entry sys_clk_timer/s1
{
address = "0x02120800";
span = "0x00000020";
}
Entry sysid/control_slave
{
address = "0x021208b8";
span = "0x00000008";
}
Entry reconfig_request_pio/s1
{
address = "0x021208a0";
span = "0x00000010";
}
Entry cpu/jtag_debug_module
{
address = "0x02120000";
span = "0x00000800";
}
Entry jtag_uart/avalon_jtag_slave
{
address = "0x021208b0";
span = "0x00000008";
}
Entry ext_flash/s1
{
address = "0x00000000";
span = "0x00800000";
}
Entry ext_ram/s1
{
address = "0x02000000";
span = "0x00100000";
}
Entry lan91c111/s1
{
address = "0x02110000";
span = "0x00010000";
}
Entry high_res_timer/s1
{
address = "0x02120820";
span = "0x00000020";
}
Entry lcd_display/control_slave
{
address = "0x02120880";
span = "0x00000010";
}
Entry uart1/s1
{
address = "0x02120840";
span = "0x00000020";
}
Entry button_pio/s1
{
address = "0x02120860";
span = "0x00000010";
}
Entry led_pio/s1
{
address = "0x02120870";
span = "0x00000010";
}
Entry seven_seg_pio/s1
{
address = "0x02120890";
span = "0x00000010";
}
Entry performance_counter/control_slave
{
address = "0x02120900";
span = "0x00000040";
}
Entry onchip_ram/s1
{
address = "0x02100000";
span = "0x00010000";
}
Entry sdram/s1
{
address = "0x01000000";
span = "0x01000000";
}
Entry dma/control_port_slave
{
address = "0x02120a00";
span = "0x00000020";
}
Entry tightly_coupled_instruction_memory/s2
{
address = "0x08000000";
span = "0x00001000";
}
Entry pll/s1
{
address = "0x00800020";
span = "0x00000020";
}
}
}
MASTER tightly_coupled_instruction_master_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "0";
Do_Stream_Writes = "0";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "28";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Is_Instruction_Master = "1";
Has_IRQ = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
PORT_WIRING
{
PORT icm0_address
{
type = "address";
width = "28";
direction = "output";
Is_Enabled = "1";
}
PORT icm0_read
{
type = "read";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT icm0_readdata
{
type = "readdata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT icm0_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT icm0_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT icm0_clken
{
type = "clken";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
MEMORY_MAP
{
Entry tightly_coupled_instruction_memory/s1
{
address = "0x08000000";
span = "0x00001000";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
cache_has_dcache = "1";
cache_dcache_size = "2048";
cache_dcache_line_size = "32";
cache_dcache_bursts = "0";
cache_dcache_ram_block_type = "AUTO";
num_tightly_coupled_data_masters = "1";
gui_num_tightly_coupled_data_masters = "1";
gui_include_tightly_coupled_data_masters = "1";
gui_omit_avalon_data_master = "0";
cache_has_icache = "1";
cache_icache_size = "4096";
cache_icache_line_size = "32";
cache_icache_ram_block_type = "AUTO";
cache_icache_bursts = "0";
num_tightly_coupled_instruction_masters = "1";
gui_num_tightly_coupled_instruction_masters = "1";
gui_include_tightly_coupled_instruction_masters = "1";
debug_level = "5";
include_oci = "1";
oci_sbi_enabled = "1";
oci_num_xbrk = "4";
oci_num_dbrk = "4";
oci_dbrk_trace = "1";
oci_dbrk_pairs = "1";
oci_onchip_trace = "1";
oci_offchip_trace = "1";
oci_data_trace = "1";
include_third_party_debug_port = "0";
oci_trace_addr_width = "7";
oci_trigger_arming = "1";
oci_debugreq_signals = "0";
oci_embedded_pll = "1";
oci_num_pm = "0";
oci_pm_width = "32";
performance_counters_present = "0";
performance_counters_width = "32";
always_encrypt = "1";
debug_simgen = "0";
activate_model_checker = "0";
activate_test_end_checker = "0";
activate_trace = "1";
activate_monitors = "1";
clear_x_bits_ld_non_bypass = "1";
bit_31_bypass_dcache = "1";
always_bypass_dcache = "0";
hdl_sim_caches_cleared = "1";
hbreak_test = "0";
allow_full_address_range = "0";
branch_prediction_type = "Dynamic";
bht_ptr_sz = "8";
bht_index_pc_only = "0";
gui_branch_prediction_type = "Automatic";
full_waveform_signals = "0";
export_pcb = "0";
avalon_debug_port_present = "0";
gui_illegal_instructions_trap = "0";
gui_illegal_memory_access_detection = "0";
illegal_mem_exc = "0";
slave_access_error_exc = "0";
division_error_exc = "0";
gui_mmu_present = "0";
process_id_num_bits = "10";
dtlb_ptr_sz = "7";
itlb_ptr_sz = "7";
dtlb_num_ways = "4";
itlb_num_ways = "4";
udtlb_num_entries = "6";
uitlb_num_entries = "4";
fast_tlb_miss_exc_slave = "";
fast_tlb_miss_exc_offset = "0x00000000";
hardware_divide_present = "0";
gui_hardware_divide_setting = "0";
hardware_multiply_present = "1";
hardware_multiply_impl = "dsp_mul";
shift_rot_impl = "dsp_shift";
gui_hardware_multiply_setting = "dsp_mul_dsp_shift";
reset_slave = "ext_flash/s1";
break_slave = "cpu/jtag_debug_module";
exc_slave = "tightly_coupled_instruction_memory/s1";
reset_offset = "0x00000000";
break_offset = "0x00000020";
exc_offset = "0x00000020";
cpu_reset = "0";
CPU_Implementation = "fast";
cpu_selection = "f";
device_family_id = "STRATIX";
address_stall_present = "0";
dsp_block_supports_shift = "0";
do_generate = "1";
cpuid_value = "0";
cpuid_sz = "1";
dont_overwrite_cpuid = "1";
allow_legacy_sdk = "1";
legacy_sdk_support = "1";
inst_addr_width = "28";
data_addr_width = "28";
asp_debug = "0";
asp_core_debug = "0";
CPU_Architecture = "nios2";
cache_icache_burst_type = "none";
include_debug = "0";
include_trace = "0";
hardware_multiply_uses_les = "0";
hardware_multiply_omits_msw = "0";
big_endian = "0";
break_slave_override = "";
break_offset_override = "0x20";
altera_show_unreleased_features = "0";
altera_show_unpublished_features = "0";
altera_internal_test = "0";
alt_log_port_base = "";
alt_log_port_type = "";
mmu_present = "0";
nmi_present = "0";
fast_intr_present = "0";
num_shadow_regs = "0";
illegal_instructions_trap = "0";
illegal_memory_access_detection = "0";
cache_omit_dcache = "0";
cache_omit_icache = "0";
omit_instruction_master = "0";
omit_data_master = "0";
ras_ptr_sz = "4";
jtb_ptr_sz = "5";
ibuf_ptr_sz = "4";
iss_trace_on = "0";
iss_trace_warning = "1";
iss_trace_info = "1";
iss_trace_disassembly = "0";
iss_trace_registers = "0";
iss_trace_instr_count = "0";
iss_software_debug = "0";
iss_software_debug_port = "9996";
iss_memory_dump_start = "";
iss_memory_dump_end = "";
Boot_Copier = "boot_loader_cfi.srec";
Boot_Copier_EPCS = "boot_loader_epcs.srec";
Boot_Copier_EPCS_SII_CIII = "boot_loader_epcs_sii_ciii.srec";
Boot_Copier_BE = "boot_loader_cfi_be.srec";
Boot_Copier_EPCS_BE = "boot_loader_epcs_be.srec";
Boot_Copier_EPCS_SII_CIII_BE = "boot_loader_epcs_sii_ciii_be.srec";
CONSTANTS
{
CONSTANT __nios_catch_irqs__
{
value = "1";
comment = "Include panic handler for all irqs (needs uart)";
}
CONSTANT __nios_use_constructors__
{
value = "1";
comment = "Call c++ static constructors";
}
CONSTANT __nios_use_small_printf__
{
value = "1";
comment = "Smaller non-ANSI printf, with no floating point";
}
CONSTANT nasys_has_icache
{
value = "1";
comment = "True if instruction cache present";
}
CONSTANT nasys_icache_size
{
value = "4096";
comment = "Size in bytes of instruction cache";
}
CONSTANT nasys_icache_line_size
{
value = "32";
comment = "Size in bytes of each icache line";
}
CONSTANT nasys_icache_line_size_log2
{
value = "5";
comment = "Log2 size in bytes of each icache line";
}
CONSTANT nasys_has_dcache
{
value = "1";
comment = "True if instruction cache present";
}
CONSTANT nasys_dcache_size
{
value = "2048";
comment = "Size in bytes of data cache";
}
CONSTANT nasys_dcache_line_size
{
value = "32";
comment = "Size in bytes of each dcache line";
}
CONSTANT nasys_dcache_line_size_log2
{
value = "5";
comment = "Log2 size in bytes of each dcache line";
}
}
license_status = "encrypted";
mainmem_slave = "sdram/s1";
datamem_slave = "sdram/s1";
maincomm_slave = "uart1/s1";
germs_monitor_id = "";
advanced_exc = "0";
}
class = "altera_nios2";
class_version = "7.07";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "pll_c0_out";
Has_Clock = "1";
Parameters_Signature = "";
Is_CPU = "1";
Instantiate_In_System_Module = "1";
Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,STRATIXIIGXLITE,STRATIXIII,CYCLONE,CYCLONEII,CYCLONEIII";
Default_Module_Name = "cpu";
Top_Level_Ports_Are_Enumerated = "1";
View
{
Settings_Summary = "Nios II/f
4-Kbyte Instruction Cache
2-Kbyte Data Cache
JTAG Debug Module
";
MESSAGES
{
}
}
}
iss_model_name = "altera_nios2";
HDL_INFO
{
PLI_Files = "";
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_test_bench.v, __PROJECT_DIRECTORY__/cpu_mult_cell.v, __PROJECT_DIRECTORY__/cpu_ext_trace_pll_module.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module_wrapper.v, __PROJECT_DIRECTORY__/cpu.vo";
Synthesis_Only_Files = "";
}
MASTER tightly_coupled_instruction_master_1
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
Is_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_instruction_master_2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
Is_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_instruction_master_3
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
Is_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER data_master2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Is_Big_Endian = "0";
}
}
MASTER tightly_coupled_data_master_1
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Is_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_data_master_2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Is_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_data_master_3
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Is_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
PORT_WIRING
{
PORT jtag_debug_trigout
{
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT jtag_debug_offchip_trace_clk
{
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT jtag_debug_offchip_trace_data
{
width = "18";
direction = "output";
Is_Enabled = "1";
}
PORT clkx2
{
width = "1";
direction = "input";
Is_Enabled = "0";
visible = "0";
}
}
SOFTWARE_COMPONENT altera_plugs_library
{
class = "altera_plugs_library";
class_version = "7.07";
WIZARD_SCRIPT_ARGUMENTS
{
CONSTANTS
{
CONSTANT PLUGS_PLUG_COUNT
{
value = "5";
comment = "Maximum number of plugs";
}
CONSTANT PLUGS_ADAPTER_COUNT
{
value = "2";
comment = "Maximum number of adapters";
}
CONSTANT PLUGS_DNS
{
value = "1";
comment = "Have routines for DNS lookups";
}
CONSTANT PLUGS_PING
{
value = "1";
comment = "Respond to icmp echo (ping) messages";
}
CONSTANT PLUGS_TCP
{
value = "1";
comment = "Support tcp in/out connections";
}
CONSTANT PLUGS_IRQ
{
value = "1";
comment = "Run at interrupte level";
}
CONSTANT PLUGS_DEBUG
{
value = "1";
comment = "Support debug routines";
}
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
}
}
SIMULATION
{
DISPLAY
{
SIGNAL aaa
{
format = "Logic";
name = "i_readdata";
radix = "hexadecimal";
}
SIGNAL aab
{
format = "Logic";
name = "i_readdatavalid";
radix = "hexadecimal";
}
SIGNAL aac
{
format = "Logic";
name = "i_waitrequest";
radix = "hexadecimal";
}
SIGNAL aad
{
format = "Logic";
name = "i_address";
radix = "hexadecimal";
}
SIGNAL aae
{
format = "Logic";
name = "i_read";
radix = "hexadecimal";
}
SIGNAL aaf
{
format = "Logic";
name = "icm0_readdata";
radix = "hexadecimal";
}
SIGNAL aag
{
format = "Logic";
name = "icm0_waitrequest";
radix = "hexadecimal";
}
SIGNAL aah
{
format = "Logic";
name = "icm0_readdatavalid";
radix = "hexadecimal";
}
SIGNAL aai
{
format = "Logic";
name = "icm0_address";
radix = "hexadecimal";
}
SIGNAL aaj
{
format = "Logic";
name = "icm0_read";
radix = "hexadecimal";
}
SIGNAL aak
{
format = "Logic";
name = "icm0_clken";
radix = "hexadecimal";
}
SIGNAL aal
{
format = "Logic";
name = "E_ci_combo_dataa";
radix = "hexadecimal";
}
SIGNAL aam
{
format = "Logic";
name = "E_ci_combo_datab";
radix = "hexadecimal";
}
SIGNAL aan
{
format = "Logic";
name = "E_ci_combo_ipending";
radix = "hexadecimal";
}
SIGNAL aao
{
format = "Logic";
name = "E_ci_combo_status";
radix = "hexadecimal";
}
SIGNAL aap
{
format = "Logic";
name = "E_ci_combo_estatus";
radix = "hexadecimal";
}
SIGNAL aaq
{
format = "Logic";
name = "E_ci_combo_n";
radix = "hexadecimal";
}
SIGNAL aar
{
format = "Logic";
name = "E_ci_combo_a";
radix = "hexadecimal";
}
SIGNAL aas
{
format = "Logic";
name = "E_ci_combo_b";
radix = "hexadecimal";
}
SIGNAL aat
{
format = "Logic";
name = "E_ci_combo_c";
radix = "hexadecimal";
}
SIGNAL aau
{
format = "Logic";
name = "E_ci_combo_readra";
radix = "hexadecimal";
}
SIGNAL aav
{
format = "Logic";
name = "E_ci_combo_readrb";
radix = "hexadecimal";
}
SIGNAL aaw
{
format = "Logic";
name = "E_ci_combo_writerc";
radix = "hexadecimal";
}
SIGNAL aax
{
format = "Logic";
name = "E_ci_combo_result";
radix = "hexadecimal";
}
SIGNAL aay
{
format = "Logic";
name = "clk";
radix = "hexadecimal";
}
SIGNAL aaz
{
format = "Logic";
name = "reset_n";
radix = "hexadecimal";
}
SIGNAL aba
{
format = "Logic";
name = "d_readdata";
radix = "hexadecimal";
}
SIGNAL abb
{
format = "Logic";
name = "d_waitrequest";
radix = "hexadecimal";
}
SIGNAL abc
{
format = "Logic";
name = "d_irq";
radix = "hexadecimal";
}
SIGNAL abd
{
format = "Logic";
name = "d_address";
radix = "hexadecimal";
}
SIGNAL abe
{
format = "Logic";
name = "d_byteenable";
radix = "hexadecimal";
}
SIGNAL abf
{
format = "Logic";
name = "d_read";
radix = "hexadecimal";
}
SIGNAL abg
{
format = "Logic";
name = "d_write";
radix = "hexadecimal";
}
SIGNAL abh
{
format = "Logic";
name = "d_writedata";
radix = "hexadecimal";
}
SIGNAL abi
{
format = "Logic";
name = "d_readdatavalid";
radix = "hexadecimal";
}
SIGNAL abj
{
format = "Logic";
name = "dcm0_readdata";
radix = "hexadecimal";
}
SIGNAL abk
{
format = "Logic";
name = "dcm0_waitrequest";
radix = "hexadecimal";
}
SIGNAL abl
{
format = "Logic";
name = "dcm0_readdatavalid";
radix = "hexadecimal";
}
SIGNAL abm
{
format = "Logic";
name = "dcm0_address";
radix = "hexadecimal";
}
SIGNAL abn
{
format = "Logic";
name = "dcm0_byteenable";
radix = "hexadecimal";
}
SIGNAL abo
{
format = "Logic";
name = "dcm0_read";
radix = "hexadecimal";
}
SIGNAL abp
{
format = "Logic";
name = "dcm0_write";
radix = "hexadecimal";
}
SIGNAL abq
{
format = "Logic";
name = "dcm0_clken";
radix = "hexadecimal";
}
SIGNAL abr
{
format = "Logic";
name = "dcm0_writedata";
radix = "hexadecimal";
}
SIGNAL abs
{
format = "Logic";
name = "the_cpu_test_bench/W_pcb";
radix = "hexadecimal";
}
SIGNAL abt
{
format = "Logic";
name = "the_cpu_test_bench/W_vinst";
radix = "ascii";
}
SIGNAL abu
{
format = "Logic";
name = "the_cpu_test_bench/W_valid";
radix = "hexadecimal";
}
SIGNAL abv
{
format = "Logic";
name = "the_cpu_test_bench/W_iw";
radix = "hexadecimal";
}
}
}
}
MODULE sys_clk_timer
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT irq
{
type = "irq";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "3";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "16";
direction = "input";
Is_Enabled = "1";
}
PORT readdata
{
type = "readdata";
width = "16";
direction = "output";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Has_IRQ = "1";
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "16";
Address_Width = "3";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x02120800";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "0";
}
Base_Address = "0x02120800";
Address_Group = "0";
}
}
class = "altera_avalon_timer";
class_version = "7.07";
iss_model_name = "altera_avalon_timer";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Top_Level_Ports_Are_Enumerated = "1";
View
{
Settings_Summary = "Timer with 10 ms timeout period.";
Is_Collapsed = "1";
MESSAGES
{
}
}
Clock_Source = "pll_c0_out";
Has_Clock = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
always_run = "0";
fixed_period = "0";
snapshot = "1";
period = "10.0";
period_units = "ms";
reset_output = "0";
timeout_pulse_output = "0";
load_value = "499999";
mult = "0.001";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sys_clk_timer.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE sysid
{
SLAVE control_slave
{
PORT_WIRING
{
PORT clock
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT address
{
type = "address";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "32";
Address_Width = "1";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x021208b8";
}
Base_Address = "0x021208b8";
Has_IRQ = "0";
Address_Group = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
class = "altera_avalon_sysid";
class_version = "7.07";
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Fixed_Module_Name = "sysid";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "pll_c0_out";
Has_Clock = "1";
View
{
Settings_Summary = "System ID (at last Generate):
2047C2A0 (unique ID tag)
46FB454B (timestamp: Wed Sep 26, 2007 @10:53 PM)";
MESSAGES
{
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
id = "541573792u";
timestamp = "1190872395u";
regenerate_values = "0";
MAKE
{
TARGET verifysysid
{
verifysysid
{
All_Depends_On = "0";
Command = "nios2-download $(JTAG_CABLE) --sidp=0x021208b8 --id=541573792 --timestamp=1190872395";
Is_Phony = "1";
Target_File = "dummy_verifysysid_file";
}
}
}
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE reconfig_request_pio
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "2";
direction = "input";
Is_Enabled = "1";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT readdata
{
type = "readdata";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "1";
Address_Width = "2";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x021208a0";
}
Base_Address = "0x021208a0";
Has_IRQ = "0";
Address_Group = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Is_Readable = "1";
Is_Writable = "1";
}
}
PORT_WIRING
{
PORT bidir_port
{
type = "export";
width = "1";
direction = "inout";
Is_Enabled = "1";
}
PORT in_port
{
direction = "input";
Is_Enabled = "0";
width = "1";
}
PORT out_port
{
direction = "output";
Is_Enabled = "0";
width = "1";
}
}
class = "altera_avalon_pio";
class_version = "7.07";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "pll_c0_out";
Has_Clock = "1";
Date_Modified = "";
View
{
MESSAGES
{
}
Settings_Summary = " 1-bit PIO using
tri-state pins with edge type NONE and interrupt source NONE
";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0";
has_tri = "1";
has_out = "0";
has_in = "0";
capture = "0";
Data_Width = "1";
edge_type = "NONE";
irq_type = "NONE";
bit_clearing_edge_register = "0";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/reconfig_request_pio.v";
Synthesis_Only_Files = "";
}
}
MODULE jtag_uart
{
SLAVE avalon_jtag_slave
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT av_irq
{
type = "irq";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT av_chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_address
{
type = "address";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_read_n
{
type = "read_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT av_write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT av_waitrequest
{
type = "waitrequest";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT dataavailable
{
type = "dataavailable";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT readyfordata
{
type = "readyfordata";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT rst_n
{
type = "reset_n";
direction = "input";
width = "1";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Has_IRQ = "1";
Bus_Type = "avalon";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "1";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "32";
Address_Width = "1";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
JTAG_Hub_Base_Id = "262254";
JTAG_Hub_Instance_Id = "0";
Connection_Limit = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x021208b0";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "1";
}
Base_Address = "0x021208b0";
Address_Group = "0";
}
}
class = "altera_avalon_jtag_uart";
class_version = "7.07";
iss_model_name = "altera_avalon_jtag_uart";
WIZARD_SCRIPT_ARGUMENTS
{
write_depth = "64";
read_depth = "64";
write_threshold = "8";
read_threshold = "8";
read_char_stream = "";
showascii = "1";
read_le = "0";
write_le = "0";
altera_show_unreleased_jtag_uart_features = "0";
}
SIMULATION
{
DISPLAY
{
SIGNAL av_chipselect
{
name = "av_chipselect";
}
SIGNAL av_address
{
name = "av_address";
radix = "hexadecimal";
}
SIGNAL av_read_n
{
name = "av_read_n";
}
SIGNAL av_readdata
{
name = "av_readdata";
radix = "hexadecimal";
}
SIGNAL av_write_n
{
name = "av_write_n";
}
SIGNAL av_writedata
{
name = "av_writedata";
radix = "hexadecimal";
}
SIGNAL av_waitrequest
{
name = "av_waitrequest";
}
SIGNAL dataavailable
{
name = "dataavailable";
}
SIGNAL readyfordata
{
name = "readyfordata";
}
SIGNAL av_irq
{
name = "av_irq";
}
}
INTERACTIVE_IN drive
{
enable = "0";
file = "_input_data_stream.dat";
mutex = "_input_data_mutex.dat";
log = "_in.log";
rate = "100";
signals = "temp,list";
exe = "nios2-terminal";
}
INTERACTIVE_OUT log
{
enable = "1";
exe = "perl -- atail-f.pl";
file = "_output_stream.dat";
radix = "ascii";
signals = "temp,list";
}
Fix_Me_Up = "";
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "pll_c0_out";
Has_Clock = "1";
Instantiate_In_System_Module = "1";
Iss_Launch_Telnet = "0";
Top_Level_Ports_Are_Enumerated = "1";
View
{
MESSAGES
{
}
Settings_Summary = "
Write Depth: 64; Write IRQ Threshold: 8
Read Depth: 64; Read IRQ Threshold: 8";
}
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE ext_ram_bus
{
SLAVE avalon_slave
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "1";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "1";
Register_Outgoing_Signals = "1";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/instruction_master
{
priority = "1";
Offset_Address = "0x00000000";
}
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x00000000";
}
MASTERED_BY dma/read_master
{
priority = "1";
Offset_Address = "0x00000000";
}
MASTERED_BY dma/write_master
{
priority = "1";
Offset_Address = "0x00000000";
}
Bridges_To = "tristate_master";
Base_Address = "N/A";
Has_IRQ = "0";
IRQ = "N/A";
Address_Group = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
MASTER tristate_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Bridges_To = "avalon_slave";
}
PORT_WIRING
{
}
MEMORY_MAP
{
Entry ext_flash/s1
{
address = "0x00000000";
span = "0x00800000";
}
Entry ext_ram/s1
{
address = "0x02000000";
span = "0x00100000";
}
Entry lan91c111/s1
{
address = "0x02110000";
span = "0x00010000";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
}
class = "altera_avalon_tri_state_bridge";
class_version = "7.07";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "pll_c0_out";
Has_Clock = "1";
Instantiate_In_System_Module = "1";
Is_Bridge = "1";
Top_Level_Ports_Are_Enumerated = "1";
View
{
MESSAGES
{
}
}
}
}
MODULE high_res_timer
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT irq
{
type = "irq";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "3";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "16";
direction = "input";
Is_Enabled = "1";
}
PORT readdata
{
type = "readdata";
width = "16";
direction = "output";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Has_IRQ = "1";
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "16";
Address_Width = "3";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x02120820";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "3";
}
Base_Address = "0x02120820";
Address_Group = "0";
}
}
class = "altera_avalon_timer";
class_version = "7.07";
iss_model_name = "altera_avalon_timer";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Top_Level_Ports_Are_Enumerated = "1";
View
{
Settings_Summary = "Timer with 10 us timeout period.";
Is_Collapsed = "1";
MESSAGES
{
}
}
Clock_Source = "pll_c0_out";
Has_Clock = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
always_run = "0";
fixed_period = "0";
snapshot = "1";
period = "10.0";
period_units = "us";
reset_output = "0";
timeout_pulse_output = "0";
load_value = "499";
mult = "0.001";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/high_res_timer.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE ext_flash
{
SLAVE s1
{
PORT_WIRING
{
PORT data
{
type = "data";
width = "8";
direction = "inout";
Is_Enabled = "1";
is_shared = "1";
}
PORT address
{
type = "address";
width = "23";
direction = "input";
Is_Enabled = "1";
is_shared = "1";
}
PORT read_n
{
type = "read_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT select_n
{
type = "chipselect_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Write_Wait_States = "160ns";
Read_Wait_States = "160ns";
Hold_Time = "40ns";
Setup_Time = "40ns";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "1";
Address_Span = "8388608";
Read_Latency = "0";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Active_CS_Through_Read_Latency = "0";
Data_Width = "8";
Address_Width = "23";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY ext_ram_bus/tristate_master
{
priority = "1";
Offset_Address = "0x00000000";
}
Base_Address = "0x00000000";
Has_IRQ = "0";
Simulation_Num_Lanes = "1";
Convert_Xs_To_0 = "1";
Address_Group = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
class = "altera_avalon_cfi_flash";
Supports_Flash_File_System = "1";
flash_reference_designator = "";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Setup_Value = "40";
Wait_Value = "160";
Hold_Value = "40";
Timing_Units = "ns";
Unit_Multiplier = "1";
Size = "8388608";
MAKE
{
MACRO
{
EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(EXT_FLASH_FLASHTARGET_TMP1:0=)";
EXT_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
PAD_DAT_FILES = "--pad=0";
}
MASTER cpu
{
MACRO
{
BOOT_COPIER = "boot_loader_cfi.srec";
CPU_CLASS = "altera_nios2";
CPU_RESET_ADDRESS = "0x0";
}
}
TARGET dat
{
ext_flash
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Post-processing to create $(notdir $@)";
Command3 = "flash2dat --infile=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --outfile=$(SIMDIR)/ext_flash.dat --base=0x00000000 --end=0x7FFFFF $(PAD_DAT_FILES) --create-lanes=0 --width=8 --relocate-input=0x00000000 ";
Dependency = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
Target_File = "$(SIMDIR)/ext_flash.dat";
}
}
TARGET delete_placeholder_warning
{
ext_flash
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET flashfiles
{
ext_flash
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Command2 = "elf2flash --input=$(ELF) --flash= --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER)$(DBL_QUOTE) --outfile=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0x7FFFFF --reset=$(CPU_RESET_ADDRESS) ";
Dependency = "$(ELF)";
Target_File = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
}
}
TARGET sym
{
ext_flash
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Post-processing to create $(notdir $@)";
Command3 = "nios2-elf-nm -n $(ELF) > $(SIMDIR)/ext_flash.sym";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/ext_flash.sym";
}
}
}
contents_info = "SIMDIR/ext_flash.dat 1190872577 ";
}
SYSTEM_BUILDER_INFO
{
Simulation_Num_Lanes = "1";
Is_Enabled = "1";
Clock_Source = "pll_c0_out";
Has_Clock = "1";
Make_Memory_Model = "1";
Instantiate_In_System_Module = "0";
Top_Level_Ports_Are_Enumerated = "1";
View
{
MESSAGES
{
}
}
}
class = "altera_avalon_cfi_flash";
class_version = "7.07";
iss_model_name = "altera_avalon_flash";
HDL_INFO
{
}
}
MODULE ext_ram
{
PORT_WIRING
{
}
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Write_Wait_States = "0ns";
Read_Wait_States = "0ns";
Hold_Time = "half";
Setup_Time = "0";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "1048576";
Read_Latency = "0";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Active_CS_Through_Read_Latency = "0";
Data_Width = "32";
Address_Width = "18";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY ext_ram_bus/tristate_master
{
priority = "1";
Offset_Address = "0x02000000";
}
Base_Address = "0x02000000";
Has_IRQ = "0";
Address_Group = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
PORT_WIRING
{
PORT data
{
type = "data";
width = "32";
direction = "inout";
Is_Enabled = "1";
is_shared = "1";
}
PORT address
{
type = "address";
width = "18";
direction = "input";
Is_Enabled = "1";
is_shared = "1";
}
PORT read_n
{
type = "read_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT be_n
{
type = "byteenable_n";
width = "4";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT select_n
{
type = "chipselect_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
}
}
iss_model_name = "altera_memory";
WIZARD_SCRIPT_ARGUMENTS
{
sram_memory_size = "1048576";
sram_memory_units = "1";
sram_data_width = "32";
simulation_model_num_lanes = "4";
MAKE
{
MACRO
{
PAD_DAT_FILES = "--pad=0";
}
TARGET dat
{
ext_ram
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Post-processing to create $(notdir $@)";
Command3 = "elf2dat --infile=$(ELF) --outfile=$(SIMDIR)/ext_ram.dat --base=0x02000000 --end=0x20FFFFF $(PAD_DAT_FILES) --create-lanes=1 --width=32 ";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/ext_ram.dat";
}
}
TARGET delete_placeholder_warning
{
ext_ram
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET sym
{
ext_ram
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Post-processing to create $(notdir $@)";
Command3 = "nios2-elf-nm -n $(ELF) > $(SIMDIR)/ext_ram.sym";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/ext_ram.sym";
}
}
}
contents_info = "SIMDIR/ext_ram_lane0.dat 1190872579 SIMDIR/ext_ram_lane3.dat 1190872579 SIMDIR/ext_ram_lane1.dat 1190872579 SIMDIR/ext_ram_lane2.dat 1190872579 SIMDIR/ext_ram.dat 1190872579 ";
}
class = "altera_nios_dev_kit_stratix_edition_sram2";
class_version = "7.07";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "pll_c0_out";
Has_Clock = "1";
Instantiate_In_System_Module = "0";
Make_Memory_Model = "1";
Default_Module_Name = "sram";
Top_Level_Ports_Are_Enumerated = "1";
View
{
MESSAGES
{
}
}
}
HDL_INFO
{
}
}
MODULE lan91c111
{
SLAVE s1
{
PORT_WIRING
{
PORT irq
{
type = "irq";
width = "1";
direction = "output";
Is_Enabled = "1";
test_bench_value = "0";
}
PORT byteenablen
{
type = "byteenable_n";
width = "4";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT address
{
type = "address";
width = "14";
direction = "input";
Is_Enabled = "1";
is_shared = "1";
}
PORT data
{
type = "data";
width = "32";
direction = "inout";
Is_Enabled = "1";
is_shared = "1";
}
PORT iow_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT ior_n
{
type = "read_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT reset
{
type = "reset";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT reset_n
{
direction = "input";
width = "1";
type = "reset_n";
Is_Enabled = "0";
}
PORT ardy
{
direction = "output";
width = "1";
type = "inhibitrequest_n";
Is_Enabled = "0";
}
}
SYSTEM_BUILDER_INFO
{
Has_IRQ = "1";
Bus_Type = "avalon_tristate";
Write_Wait_States = "175ns";
Read_Wait_States = "175ns";
Hold_Time = "5ns";
Setup_Time = "10ns";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Active_CS_Through_Read_Latency = "0";
Data_Width = "32";
Address_Width = "14";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY ext_ram_bus/tristate_master
{
priority = "1";
Offset_Address = "0x02110000";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "6";
}
Base_Address = "0x02110000";
Instantiate_In_System_Module = "0";
Is_Bus_Master = "0";
Uses_Tri_State_Data_Bus = "1";
Date_Modified = "2002.03.19.10:51:51";
Tri_State_Data_Bus = "--unknown--";
Address_Group = "0";
}
}
class = "altera_avalon_lan91c111";
class_version = "7.07";
WIZARD_SCRIPT_ARGUMENTS
{
Is_Ethernet_Mac = "1";
CONSTANTS
{
CONSTANT LAN91C111_REGISTERS_OFFSET
{
value = "768";
comment = "offset 0 or 0x300, depending on address bus wiring";
}
CONSTANT LAN91C111_DATA_BUS_WIDTH
{
value = "32";
comment = "width 16 or 32, depending on data bus wiring";
}
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "pll_c0_out";
Has_Clock = "1";
Instantiate_In_System_Module = "0";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
View
{
MESSAGES
{
}
}
}
PORT_WIRING
{
}
}
MODULE lcd_display
{
SLAVE control_slave
{
PORT_WIRING
{
PORT address
{
type = "address";
width = "2";
direction = "input";
Is_Enabled = "1";
}
PORT begintransfer
{
type = "begintransfer";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT read
{
type = "read";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT readdata
{
type = "readdata";
width = "8";
direction = "output";
Is_Enabled = "1";
}
PORT write
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "8";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "250ns";
Read_Wait_States = "250ns";
Hold_Time = "250ns";
Setup_Time = "250ns";
Is_Printable_Device = "1";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "8";
Address_Width = "2";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x02120880";
}
Base_Address = "0x02120880";
Has_IRQ = "0";
Address_Group = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
PORT_WIRING
{
PORT LCD_data
{
type = "export";
width = "8";
direction = "inout";
Is_Enabled = "1";
}
PORT LCD_E
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT LCD_RS
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT LCD_RW
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
}
class = "altera_avalon_lcd_16207";
class_version = "7.07";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "pll_c0_out";
Has_Clock = "1";
Date_Modified = "";
Instantiate_In_System_Module = "1";
Top_Level_Ports_Are_Enumerated = "1";
View
{
MESSAGES
{
}
}
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/lcd_display.v";
Synthesis_Only_Files = "";
}
}
MODULE uart1
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT irq
{
type = "irq";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "3";
direction = "input";
Is_Enabled = "1";
}
PORT begintransfer
{
type = "begintransfer";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT read_n
{
type = "read_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "16";
direction = "input";
Is_Enabled = "1";
}
PORT readdata
{
type = "readdata";
width = "16";
direction = "output";
Is_Enabled = "1";
}
PORT dataavailable
{
type = "dataavailable";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT readyfordata
{
type = "readyfordata";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Has_IRQ = "1";
Bus_Type = "avalon";
Write_Wait_States = "1cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "1";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "16";
Address_Width = "3";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x02120840";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "4";
}
Base_Address = "0x02120840";
Address_Group = "0";
}
}
PORT_WIRING
{
PORT rxd
{
type = "export";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT txd
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT cts_n
{
direction = "input";
width = "1";
Is_Enabled = "0";
}
PORT rts_n
{
direction = "output";
width = "1";
Is_Enabled = "0";
}
}
class = "altera_avalon_uart";
class_version = "7.07";
iss_model_name = "altera_avalon_uart";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Iss_Launch_Telnet = "0";
Top_Level_Ports_Are_Enumerated = "1";
View
{
Settings_Summary = "8-bit UART with 115200 baud,
1 stop bits and N parity";
Is_Collapsed = "1";
MESSAGES
{
}
}
Clock_Source = "pll_c0_out";
Has_Clock = "1";
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = " Bus Interface";
format = "Divider";
}
SIGNAL b
{
name = "chipselect";
}
SIGNAL c
{
name = "address";
radix = "hexadecimal";
}
SIGNAL d
{
name = "writedata";
radix = "hexadecimal";
}
SIGNAL e
{
name = "readdata";
radix = "hexadecimal";
}
SIGNAL f
{
name = " Internals";
format = "Divider";
}
SIGNAL g
{
name = "tx_ready";
}
SIGNAL h
{
name = "tx_data";
radix = "ascii";
}
SIGNAL i
{
name = "rx_char_ready";
}
SIGNAL j
{
name = "rx_data";
radix = "ascii";
}
}
INTERACTIVE_OUT log
{
enable = "0";
file = "_log_module.txt";
radix = "ascii";
signals = "temp,list";
exe = "perl -- tail-f.pl";
}
INTERACTIVE_IN drive
{
enable = "0";
file = "_input_data_stream.dat";
mutex = "_input_data_mutex.dat";
log = "_in.log";
rate = "100";
signals = "temp,list";
exe = "perl -- uart.pl";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
baud = "115200";
data_bits = "8";
fixed_baud = "1";
parity = "N";
stop_bits = "1";
use_cts_rts = "0";
use_eop_register = "0";
sim_true_baud = "0";
sim_char_stream = "";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart1.v";
Synthesis_Only_Files = "";
}
}
MODULE button_pio
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT irq
{
type = "irq";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "2";
direction = "input";
Is_Enabled = "1";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "4";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT readdata
{
type = "readdata";
width = "4";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Has_IRQ = "1";
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "4";
Address_Width = "2";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x02120860";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "2";
}
Base_Address = "0x02120860";
Address_Group = "0";
Is_Readable = "1";
Is_Writable = "1";
}
}
PORT_WIRING
{
PORT in_port
{
type = "export";
width = "4";
direction = "input";
Is_Enabled = "1";
test_bench_value = "15";
}
PORT out_port
{
direction = "output";
Is_Enabled = "0";
width = "4";
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "4";
}
}
class = "altera_avalon_pio";
class_version = "7.07";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "pll_c0_out";
Has_Clock = "1";
Date_Modified = "";
View
{
MESSAGES
{
}
Settings_Summary = " 4-bit PIO using
input pins with edge type ANY and interrupt source EDGE
";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "1";
Driven_Sim_Value = "15";
has_tri = "0";
has_out = "0";
has_in = "1";
capture = "1";
Data_Width = "4";
edge_type = "ANY";
irq_type = "EDGE";
bit_clearing_edge_register = "0";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/button_pio.v";
Synthesis_Only_Files = "";
}
}
MODULE led_pio
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "2";
direction = "input";
Is_Enabled = "1";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "8";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "8";
Address_Width = "2";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x02120870";
}
Base_Address = "0x02120870";
Has_IRQ = "0";
Address_Group = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Is_Readable = "0";
Is_Writable = "1";
}
}
PORT_WIRING
{
PORT out_port
{
type = "export";
width = "8";
direction = "output";
Is_Enabled = "1";
}
PORT in_port
{
direction = "input";
Is_Enabled = "0";
width = "8";
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "8";
}
}
class = "altera_avalon_pio";
class_version = "7.07";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "pll_c0_out";
Has_Clock = "1";
Date_Modified = "";
View
{
MESSAGES
{
}
Settings_Summary = " 8-bit PIO using
output pins";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0";
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
Data_Width = "8";
edge_type = "NONE";
irq_type = "NONE";
bit_clearing_edge_register = "0";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/led_pio.v";
Synthesis_Only_Files = "";
}
}
MODULE seven_seg_pio
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "2";
direction = "input";
Is_Enabled = "1";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "16";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "16";
Address_Width = "2";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x02120890";
}
Base_Address = "0x02120890";
Has_IRQ = "0";
Address_Group = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Is_Readable = "0";
Is_Writable = "1";
}
}
PORT_WIRING
{
PORT out_port
{
type = "export";
width = "16";
direction = "output";
Is_Enabled = "1";
}
PORT in_port
{
direction = "input";
Is_Enabled = "0";
width = "16";
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "16";
}
}
class = "altera_avalon_pio";
class_version = "7.07";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "pll_c0_out";
Has_Clock = "1";
Date_Modified = "";
View
{
MESSAGES
{
}
Settings_Summary = " 16-bit PIO using
output pins";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0";
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
Data_Width = "16";
edge_type = "NONE";
irq_type = "NONE";
bit_clearing_edge_register = "0";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/seven_seg_pio.v";
Synthesis_Only_Files = "";
}
}
MODULE tightly_coupled_instruction_memory
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT address
{
type = "address";
width = "10";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT clken
{
type = "clken";
width = "1";
direction = "input";
Is_Enabled = "1";
default_value = "1'b1";
}
PORT read
{
type = "read";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT write
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT debugaccess
{
type = "debugaccess";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT byteenable
{
type = "byteenable";
width = "4";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "0cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "4096";
Read_Latency = "1";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "32";
Address_Width = "10";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/tightly_coupled_instruction_master_0
{
priority = "1";
Offset_Address = "0x08000000";
}
Clock_Source = "pll_c0_out";
Has_Clock = "1";
Base_Address = "0x08000000";
Address_Group = "0";
Has_IRQ = "0";
Is_Channel = "1";
Is_Writable = "1";
}
}
SLAVE s2
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT address2
{
type = "address";
width = "10";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect2
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT clken2
{
type = "clken";
width = "1";
direction = "input";
Is_Enabled = "1";
default_value = "1'b1";
}
PORT read2
{
type = "read";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT readdata2
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT write2
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata2
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT debugaccess2
{
type = "debugaccess";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT byteenable2
{
type = "byteenable";
width = "4";
direction = "input";
Is_Enabled = "1";
}
PORT clk2
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "0cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "4096";
Read_Latency = "1";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "32";
Address_Width = "10";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x08000000";
}
Clock_Source = "pll_c0_out";
Has_Clock = "1";
Base_Address = "0x08000000";
Address_Group = "0";
Has_IRQ = "0";
Is_Channel = "1";
Is_Writable = "1";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
iss_model_name = "altera_memory";
WIZARD_SCRIPT_ARGUMENTS
{
allow_mram_sim_contents_only_file = "0";
ram_block_type = "M4K";
init_contents_file = "tightly_coupled_instruction_memory";
non_default_init_file_enabled = "0";
gui_ram_block_type = "Automatic";
Writeable = "1";
dual_port = "1";
Size_Value = "4096";
Size_Multiple = "1";
use_shallow_mem_blocks = "0";
init_mem_content = "1";
allow_in_system_memory_content_editor = "0";
instance_id = "NONE";
ignore_auto_block_type_assignment = "1";
MAKE
{
MACRO
{
PAD_DAT_FILES = "--pad=0";
}
TARGET dat
{
tightly_coupled_instruction_memory
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Post-processing to create $(notdir $@)";
Command3 = "elf2dat --infile=$(ELF) --outfile=$(SIMDIR)/tightly_coupled_instruction_memory.dat --base=0x08000000 --end=0x8000FFF $(PAD_DAT_FILES) --create-lanes=0 --width=32 ";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/tightly_coupled_instruction_memory.dat";
}
}
TARGET delete_placeholder_warning
{
tightly_coupled_instruction_memory
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET hex
{
tightly_coupled_instruction_memory
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Command2 = "elf2hex $(ELF) 0x08000000 0x8000FFF --width=32 $(QUARTUS_PROJECT_DIR)/tightly_coupled_instruction_memory.hex --create-lanes=0 ";
Dependency = "$(ELF)";
Target_File = "$(QUARTUS_PROJECT_DIR)/tightly_coupled_instruction_memory.hex";
}
}
TARGET sym
{
tightly_coupled_instruction_memory
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Post-processing to create $(notdir $@)";
Command3 = "nios2-elf-nm -n $(ELF) > $(SIMDIR)/tightly_coupled_instruction_memory.sym";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/tightly_coupled_instruction_memory.sym";
}
}
}
contents_info = "SIMDIR/tightly_coupled_instruction_memory.dat 1190872595 QUARTUS_PROJECT_DIR/tightly_coupled_instruction_memory.hex 1190872595 ";
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = "chipselect";
conditional = "1";
}
SIGNAL c
{
name = "address";
radix = "hexadecimal";
}
SIGNAL d
{
name = "byteenable";
radix = "binary";
conditional = "1";
}
SIGNAL e
{
name = "readdata";
radix = "hexadecimal";
}
SIGNAL b
{
name = "write";
conditional = "1";
}
SIGNAL f
{
name = "writedata";
radix = "hexadecimal";
conditional = "1";
}
SIGNAL g
{
name = "chipselect2";
conditional = "1";
}
SIGNAL i
{
name = "address2";
radix = "hexadecimal";
}
SIGNAL j
{
name = "byteenable2";
radix = "binary";
conditional = "1";
}
SIGNAL k
{
name = "readdata2";
radix = "hexadecimal";
}
SIGNAL h
{
name = "write2";
conditional = "1";
}
SIGNAL l
{
name = "writedata2";
radix = "hexadecimal";
conditional = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "onchip_memory";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
MESSAGES
{
}
}
}
class = "altera_avalon_onchip_memory2";
class_version = "7.07";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/tightly_coupled_instruction_memory.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE tightly_coupled_data_memory
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT address
{
type = "address";
width = "11";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT clken
{
type = "clken";
width = "1";
direction = "input";
Is_Enabled = "1";
default_value = "1'b1";
}
PORT read
{
type = "read";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT write
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT debugaccess
{
type = "debugaccess";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT byteenable
{
type = "byteenable";
width = "4";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "0cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "8192";
Read_Latency = "1";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "32";
Address_Width = "11";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/tightly_coupled_data_master_0
{
priority = "1";
Offset_Address = "0x08002000";
}
Clock_Source = "pll_c0_out";
Has_Clock = "1";
Base_Address = "0x08002000";
Address_Group = "0";
Has_IRQ = "0";
Is_Channel = "1";
Is_Writable = "1";
}
}
SLAVE s2
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT address2
{
type = "address";
width = "11";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect2
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT clken2
{
type = "clken";
width = "1";
direction = "input";
Is_Enabled = "1";
default_value = "1'b1";
}
PORT read2
{
type = "read";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT readdata2
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT write2
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata2
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT debugaccess2
{
type = "debugaccess";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT byteenable2
{
type = "byteenable";
width = "4";
direction = "input";
Is_Enabled = "1";
}
PORT clk2
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "0cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "8192";
Read_Latency = "1";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "32";
Address_Width = "11";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY dma/read_master
{
priority = "1";
Offset_Address = "0x08002000";
}
MASTERED_BY dma/write_master
{
priority = "1";
Offset_Address = "0x08002000";
}
Clock_Source = "pll_c0_out";
Has_Clock = "1";
Base_Address = "0x08002000";
Address_Group = "0";
Has_IRQ = "0";
Is_Channel = "1";
Is_Writable = "1";
}
}
iss_model_name = "altera_memory";
WIZARD_SCRIPT_ARGUMENTS
{
allow_mram_sim_contents_only_file = "0";
ram_block_type = "M4K";
init_contents_file = "tightly_coupled_data_memory";
non_default_init_file_enabled = "0";
gui_ram_block_type = "Automatic";
Writeable = "1";
dual_port = "1";
Size_Value = "8192";
Size_Multiple = "1";
use_shallow_mem_blocks = "0";
init_mem_content = "1";
allow_in_system_memory_content_editor = "0";
instance_id = "NONE";
ignore_auto_block_type_assignment = "1";
MAKE
{
MACRO
{
PAD_DAT_FILES = "--pad=0";
}
TARGET dat
{
tightly_coupled_data_memory
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Post-processing to create $(notdir $@)";
Command3 = "elf2dat --infile=$(ELF) --outfile=$(SIMDIR)/tightly_coupled_data_memory.dat --base=0x08002000 --end=0x8003FFF $(PAD_DAT_FILES) --create-lanes=0 --width=32 ";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/tightly_coupled_data_memory.dat";
}
}
TARGET delete_placeholder_warning
{
tightly_coupled_data_memory
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET hex
{
tightly_coupled_data_memory
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Command2 = "elf2hex $(ELF) 0x08002000 0x8003FFF --width=32 $(QUARTUS_PROJECT_DIR)/tightly_coupled_data_memory.hex --create-lanes=0 ";
Dependency = "$(ELF)";
Target_File = "$(QUARTUS_PROJECT_DIR)/tightly_coupled_data_memory.hex";
}
}
TARGET sym
{
tightly_coupled_data_memory
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Post-processing to create $(notdir $@)";
Command3 = "nios2-elf-nm -n $(ELF) > $(SIMDIR)/tightly_coupled_data_memory.sym";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/tightly_coupled_data_memory.sym";
}
}
}
contents_info = "SIMDIR/tightly_coupled_data_memory.dat 1190872597 QUARTUS_PROJECT_DIR/tightly_coupled_data_memory.hex 1190872597 ";
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = "chipselect";
conditional = "1";
}
SIGNAL c
{
name = "address";
radix = "hexadecimal";
}
SIGNAL d
{
name = "byteenable";
radix = "binary";
conditional = "1";
}
SIGNAL e
{
name = "readdata";
radix = "hexadecimal";
}
SIGNAL b
{
name = "write";
conditional = "1";
}
SIGNAL f
{
name = "writedata";
radix = "hexadecimal";
conditional = "1";
}
SIGNAL g
{
name = "chipselect2";
conditional = "1";
}
SIGNAL i
{
name = "address2";
radix = "hexadecimal";
}
SIGNAL j
{
name = "byteenable2";
radix = "binary";
conditional = "1";
}
SIGNAL k
{
name = "readdata2";
radix = "hexadecimal";
}
SIGNAL h
{
name = "write2";
conditional = "1";
}
SIGNAL l
{
name = "writedata2";
radix = "hexadecimal";
conditional = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "onchip_memory";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
MESSAGES
{
}
}
}
class = "altera_avalon_onchip_memory2";
class_version = "7.07";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/tightly_coupled_data_memory.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE performance_counter
{
SLAVE control_slave
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "4";
direction = "input";
Is_Enabled = "1";
}
PORT begintransfer
{
type = "begintransfer";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT write
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "0cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "1";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "32";
Address_Width = "4";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x02120900";
}
Base_Address = "0x02120900";
Has_IRQ = "0";
Address_Group = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
how_many_sections = "3";
}
class = "altera_avalon_performance_counter";
class_version = "7.07";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "pll_c0_out";
Has_Clock = "1";
Date_Modified = "";
Instantiate_In_System_Module = "1";
Top_Level_Ports_Are_Enumerated = "1";
View
{
MESSAGES
{
}
}
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/performance_counter.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE bswap
{
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "nios_custom_instruction";
Data_Width = "32";
Address_Width = "0";
Is_Custom_Instruction = "1";
Is_Enabled = "1";
Has_Base_Address = "1";
Base_Address = "0x00000000";
ci_macro_name = "bitswap";
ci_operands = "1";
ci_cycles = "1";
ci_inst_type = "combinatorial";
MASTERED_BY cpu/custom_instruction_master
{
priority = "1";
}
IRQ_MASTER cpu/custom_instruction_master
{
IRQ_Number = "NC";
}
Is_Visible = "0";
Address_Group = "0";
}
PORT_WIRING
{
PORT dataa
{
type = "dataa";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT datab
{
type = "datab";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT result
{
type = "result";
width = "32";
direction = "output";
Is_Enabled = "1";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Module_Name = "bitswap_instruction_unit";
Synthesize_Imported_HDL = "1";
ci_macro_name = "bswap";
ci_operands = "1";
ci_cycles = "1";
ci_has_prefix = "0";
ci_inst_type = "combinatorial";
}
SYSTEM_BUILDER_INFO
{
Is_Custom_Instruction = "1";
Is_Enabled = "1";
Date_Modified = "";
Is_Visible = "0";
Instantiate_In_System_Module = "1";
Clock_Source = "pll_c0_out";
View
{
MESSAGES
{
}
}
}
class = "altera_nios_custom_instr_bitswap";
class_version = "7.07";
iss_model_name = "nios2_custom_instruction";
HDL_INFO
{
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/bswap.v";
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE interrupt_vector
{
SLAVE interrupt_vector
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "nios_custom_instruction";
Data_Width = "32";
Address_Width = "0";
Is_Custom_Instruction = "1";
Is_Enabled = "1";
Has_Base_Address = "1";
Base_Address = "0x00000001";
ci_macro_name = "interrupt_vector";
ci_operands = "0";
ci_cycles = "1";
ci_inst_type = "combinatorial";
MASTERED_BY cpu/custom_instruction_master
{
priority = "1";
}
IRQ_MASTER cpu/custom_instruction_master
{
IRQ_Number = "NC";
}
Is_Visible = "0";
required_ci_macro_name = "interrupt_vector";
Address_Group = "0";
}
PORT_WIRING
{
PORT result
{
type = "result";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT estatus
{
Is_Enabled = "1";
direction = "input";
type = "estatus";
width = "1";
}
PORT ipending
{
Is_Enabled = "1";
direction = "input";
type = "ipending";
width = "32";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Module_Name = "interrupt_vector_instruction_unit";
Synthesize_Imported_HDL = "1";
}
SYSTEM_BUILDER_INFO
{
Is_Custom_Instruction = "1";
Is_Enabled = "1";
Date_Modified = "";
Is_Visible = "0";
Instantiate_In_System_Module = "1";
Clock_Source = "pll_c0_out";
View
{
MESSAGES
{
}
}
}
class = "altera_nios_custom_instr_interrupt_vector";
class_version = "7.07";
iss_model_name = "nios2_custom_instruction";
HDL_INFO
{
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/interrupt_vector.v";
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE onchip_ram
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT address
{
type = "address";
width = "14";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT clken
{
type = "clken";
width = "1";
direction = "input";
Is_Enabled = "1";
default_value = "1'b1";
}
PORT read
{
type = "read";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT write
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT debugaccess
{
type = "debugaccess";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT byteenable
{
type = "byteenable";
width = "4";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "0cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "65536";
Read_Latency = "1";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "32";
Address_Width = "14";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x02100000";
}
MASTERED_BY cpu/instruction_master
{
priority = "1";
Offset_Address = "0x02100000";
}
MASTERED_BY dma/read_master
{
priority = "1";
Offset_Address = "0x02100000";
}
MASTERED_BY dma/write_master
{
priority = "1";
Offset_Address = "0x02100000";
}
Base_Address = "0x02100000";
Address_Group = "0";
Has_IRQ = "0";
Is_Channel = "1";
Is_Writable = "1";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
iss_model_name = "altera_memory";
WIZARD_SCRIPT_ARGUMENTS
{
allow_mram_sim_contents_only_file = "0";
ram_block_type = "M-RAM";
init_contents_file = "onchip_ram";
non_default_init_file_enabled = "0";
gui_ram_block_type = "Automatic";
Writeable = "1";
dual_port = "0";
Size_Value = "65536";
Size_Multiple = "1";
use_shallow_mem_blocks = "0";
init_mem_content = "1";
allow_in_system_memory_content_editor = "0";
instance_id = "NONE";
ignore_auto_block_type_assignment = "1";
MAKE
{
MACRO
{
PAD_DAT_FILES = "--pad=0";
}
TARGET dat
{
onchip_ram
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Post-processing to create $(notdir $@)";
Command3 = "elf2dat --infile=$(ELF) --outfile=$(SIMDIR)/onchip_ram.dat --base=0x02100000 --end=0x210FFFF $(PAD_DAT_FILES) --create-lanes=0 --width=32 ";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/onchip_ram.dat";
}
}
TARGET delete_placeholder_warning
{
onchip_ram
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET hex
{
onchip_ram
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Command2 = "elf2hex $(ELF) 0x02100000 0x210FFFF --width=32 $(QUARTUS_PROJECT_DIR)/onchip_ram.hex --create-lanes=0 ";
Dependency = "$(ELF)";
Target_File = "$(QUARTUS_PROJECT_DIR)/onchip_ram.hex";
}
}
TARGET sym
{
onchip_ram
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Post-processing to create $(notdir $@)";
Command3 = "nios2-elf-nm -n $(ELF) > $(SIMDIR)/onchip_ram.sym";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/onchip_ram.sym";
}
}
}
contents_info = "QUARTUS_PROJECT_DIR/onchip_ram.hex 1190872608 SIMDIR/onchip_ram.dat 1190872608 ";
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = "chipselect";
conditional = "1";
}
SIGNAL c
{
name = "address";
radix = "hexadecimal";
}
SIGNAL d
{
name = "byteenable";
radix = "binary";
conditional = "1";
}
SIGNAL e
{
name = "readdata";
radix = "hexadecimal";
}
SIGNAL b
{
name = "write";
conditional = "1";
}
SIGNAL f
{
name = "writedata";
radix = "hexadecimal";
conditional = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "onchip_memory";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "pll_c0_out";
Has_Clock = "1";
View
{
MESSAGES
{
}
}
}
class = "altera_avalon_onchip_memory2";
class_version = "7.07";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/onchip_ram.v";
Synthesis_Only_Files = "";
}
SLAVE s2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Memory_Device = "1";
Address_Group = "0";
Address_Alignment = "dynamic";
Address_Width = "14";
Data_Width = "32";
Has_IRQ = "0";
Read_Wait_States = "0";
Write_Wait_States = "0";
Address_Span = "65536";
Read_Latency = "1";
Is_Channel = "1";
Is_Enabled = "0";
Is_Writable = "1";
}
}
PORT_WIRING
{
}
}
MODULE sdram
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT az_addr
{
type = "address";
width = "22";
direction = "input";
Is_Enabled = "1";
}
PORT az_be_n
{
type = "byteenable_n";
width = "4";
direction = "input";
Is_Enabled = "1";
}
PORT az_cs
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT az_data
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT az_rd_n
{
type = "read_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT az_wr_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT za_data
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT za_valid
{
type = "readdatavalid";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT za_waitrequest
{
type = "waitrequest";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT zs_addr
{
direction = "output";
width = "12";
Is_Enabled = "1";
}
PORT zs_ba
{
direction = "output";
width = "2";
Is_Enabled = "1";
}
PORT zs_cas_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_cke
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_cs_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_dq
{
direction = "inout";
width = "32";
Is_Enabled = "1";
}
PORT zs_dqm
{
direction = "output";
width = "4";
Is_Enabled = "1";
}
PORT zs_ras_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_we_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "16777216";
Read_Latency = "0";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "7";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "32";
Address_Width = "22";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/instruction_master
{
priority = "8";
Offset_Address = "0x01000000";
}
MASTERED_BY cpu/data_master
{
priority = "8";
Offset_Address = "0x01000000";
}
MASTERED_BY dma/read_master
{
priority = "8";
Offset_Address = "0x01000000";
}
MASTERED_BY dma/write_master
{
priority = "8";
Offset_Address = "0x01000000";
}
Base_Address = "0x01000000";
Has_IRQ = "0";
Simulation_Num_Lanes = "1";
Address_Group = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
PORT_WIRING
{
PORT zs_addr
{
type = "zs_addr";
width = "12";
direction = "output";
Is_Enabled = "0";
}
PORT zs_ba
{
type = "zs_ba";
width = "2";
direction = "output";
Is_Enabled = "0";
}
PORT zs_cas_n
{
type = "zs_cas_n";
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT zs_cke
{
type = "zs_cke";
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT zs_cs_n
{
type = "zs_cs_n";
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT zs_dq
{
type = "zs_dq";
width = "32";
direction = "output";
Is_Enabled = "0";
}
PORT zs_dqm
{
type = "zs_dqm";
width = "4";
direction = "output";
Is_Enabled = "0";
}
PORT zs_ras_n
{
type = "zs_ras_n";
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT zs_we_n
{
type = "zs_we_n";
width = "1";
direction = "output";
Is_Enabled = "0";
}
}
iss_model_name = "altera_memory";
WIZARD_SCRIPT_ARGUMENTS
{
register_data_in = "1";
sim_model_base = "1";
sdram_data_width = "32";
sdram_addr_width = "12";
sdram_row_width = "12";
sdram_col_width = "8";
sdram_num_chipselects = "1";
sdram_num_banks = "4";
refresh_period = "15.625";
powerup_delay = "100.0";
cas_latency = "3";
t_rfc = "70.0";
t_rp = "20.0";
t_mrd = "3";
t_rcd = "20.0";
t_ac = "5.5";
t_wr = "14.0";
init_refresh_commands = "2";
init_nop_delay = "0.0";
shared_data = "0";
sdram_bank_width = "2";
tristate_bridge_slave = "";
starvation_indicator = "0";
is_initialized = "1";
MAKE
{
MACRO
{
PAD_DAT_FILES = "--pad=0";
}
TARGET dat
{
sdram
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Post-processing to create $(notdir $@)";
Command3 = "elf2dat --infile=$(ELF) --outfile=$(SIMDIR)/sdram.dat --base=0x01000000 --end=0x1FFFFFF $(PAD_DAT_FILES) --create-lanes=0 --width=32 ";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/sdram.dat";
}
}
TARGET delete_placeholder_warning
{
sdram
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET sym
{
sdram
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Post-processing to create $(notdir $@)";
Command3 = "nios2-elf-nm -n $(ELF) > $(SIMDIR)/sdram.sym";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/sdram.sym";
}
}
}
contents_info = "SIMDIR/sdram.dat 1190872611 ";
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = "az_addr";
radix = "hexadecimal";
}
SIGNAL b
{
name = "az_be_n";
radix = "hexadecimal";
}
SIGNAL c
{
name = "az_cs";
}
SIGNAL d
{
name = "az_data";
radix = "hexadecimal";
}
SIGNAL e
{
name = "az_rd_n";
}
SIGNAL f
{
name = "az_wr_n";
}
SIGNAL h
{
name = "za_data";
radix = "hexadecimal";
}
SIGNAL i
{
name = "za_valid";
}
SIGNAL j
{
name = "za_waitrequest";
}
SIGNAL l
{
name = "CODE";
radix = "ascii";
}
SIGNAL g
{
name = "clk";
}
SIGNAL k
{
name = "za_cannotrefresh";
suppress = "1";
}
SIGNAL m
{
name = "zs_addr";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL n
{
name = "zs_ba";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL o
{
name = "zs_cs_n";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL p
{
name = "zs_ras_n";
suppress = "0";
}
SIGNAL q
{
name = "zs_cas_n";
suppress = "0";
}
SIGNAL r
{
name = "zs_we_n";
suppress = "0";
}
SIGNAL s
{
name = "zs_dq";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL t
{
name = "zs_dqm";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL u
{
name = "zt_addr";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL v
{
name = "zt_ba";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL w
{
name = "zt_oe";
suppress = "1";
}
SIGNAL x
{
name = "zt_cke";
suppress = "1";
}
SIGNAL y
{
name = "zt_chipselect";
suppress = "1";
}
SIGNAL z0
{
name = "zt_lock_n";
suppress = "1";
}
SIGNAL z1
{
name = "zt_ras_n";
suppress = "1";
}
SIGNAL z2
{
name = "zt_cas_n";
suppress = "1";
}
SIGNAL z3
{
name = "zt_we_n";
suppress = "1";
}
SIGNAL z4
{
name = "zt_cs_n";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL z5
{
name = "zt_dqm";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL z6
{
name = "zt_data";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL z7
{
name = "tz_data";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL z8
{
name = "tz_waitrequest";
suppress = "1";
}
}
Fix_Me_Up = "";
PORT_WIRING
{
PORT clk
{
Is_Enabled = "1";
direction = "input";
width = "1";
}
PORT zs_addr
{
Is_Enabled = "1";
direction = "input";
width = "12";
}
PORT zs_ba
{
Is_Enabled = "1";
direction = "input";
width = "2";
}
PORT zs_cas_n
{
Is_Enabled = "1";
direction = "input";
width = "1";
}
PORT zs_cke
{
Is_Enabled = "1";
direction = "input";
width = "1";
}
PORT zs_cs_n
{
Is_Enabled = "1";
direction = "input";
width = "1";
}
PORT zs_dq
{
Is_Enabled = "1";
direction = "inout";
width = "32";
}
PORT zs_dqm
{
Is_Enabled = "1";
direction = "input";
width = "4";
}
PORT zs_ras_n
{
Is_Enabled = "1";
direction = "input";
width = "1";
}
PORT zs_we_n
{
Is_Enabled = "1";
direction = "input";
width = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "sdram";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "pll_c0_out";
Has_Clock = "1";
Disable_Simulation_Port_Wiring = "0";
View
{
MESSAGES
{
}
Settings_Summary = "4194304 x 32
Memory size: 16 MBytes
128 MBits
";
}
}
class = "altera_avalon_new_sdram_controller";
class_version = "7.07";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sdram.v, __PROJECT_DIRECTORY__/sdram_test_component.v";
Synthesis_Only_Files = "";
}
}
MODULE dma
{
SLAVE control_port_slave
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT dma_ctl_irq
{
type = "irq";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT dma_ctl_address
{
type = "address";
width = "3";
direction = "input";
Is_Enabled = "1";
}
PORT dma_ctl_chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT dma_ctl_readdata
{
type = "readdata";
width = "28";
direction = "output";
Is_Enabled = "1";
}
PORT dma_ctl_readyfordata
{
type = "readyfordata";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT dma_ctl_write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT dma_ctl_writedata
{
type = "writedata";
width = "28";
direction = "input";
Is_Enabled = "1";
}
PORT system_reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Has_IRQ = "1";
Bus_Type = "avalon";
Write_Wait_States = "1cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "28";
Address_Width = "3";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x02120a00";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "7";
}
Base_Address = "0x02120a00";
Address_Group = "0";
}
}
MASTER write_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "0";
Do_Stream_Writes = "1";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "28";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Is_Readable = "0";
Is_Writable = "1";
}
PORT_WIRING
{
PORT write_address
{
type = "address";
width = "28";
direction = "output";
Is_Enabled = "1";
}
PORT write_byteenable
{
type = "byteenable";
width = "4";
direction = "output";
Is_Enabled = "1";
}
PORT write_chipselect
{
type = "chipselect";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT write_endofpacket
{
type = "endofpacket";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT write_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT write_write_n
{
type = "write_n";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT write_writedata
{
type = "writedata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
}
MEMORY_MAP
{
Entry tightly_coupled_data_memory/s2
{
address = "0x08002000";
span = "0x00002000";
}
Entry ext_flash/s1
{
address = "0x00000000";
span = "0x00800000";
}
Entry ext_ram/s1
{
address = "0x02000000";
span = "0x00100000";
}
Entry lan91c111/s1
{
address = "0x02110000";
span = "0x00010000";
}
Entry sdram/s1
{
address = "0x01000000";
span = "0x01000000";
}
Entry onchip_ram/s1
{
address = "0x02100000";
span = "0x00010000";
}
}
}
MASTER read_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "1";
Do_Stream_Writes = "0";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "28";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Is_Readable = "1";
Is_Writable = "0";
}
PORT_WIRING
{
PORT read_address
{
type = "address";
width = "28";
direction = "output";
Is_Enabled = "1";
}
PORT read_chipselect
{
type = "chipselect";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT read_endofpacket
{
type = "endofpacket";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT read_flush
{
type = "flush";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT read_read_n
{
type = "read_n";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT read_readdata
{
type = "readdata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT read_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT read_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
MEMORY_MAP
{
Entry tightly_coupled_data_memory/s2
{
address = "0x08002000";
span = "0x00002000";
}
Entry ext_flash/s1
{
address = "0x00000000";
span = "0x00800000";
}
Entry ext_ram/s1
{
address = "0x02000000";
span = "0x00100000";
}
Entry lan91c111/s1
{
address = "0x02110000";
span = "0x00010000";
}
Entry sdram/s1
{
address = "0x01000000";
span = "0x01000000";
}
Entry onchip_ram/s1
{
address = "0x02100000";
span = "0x00010000";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
readaddress_reset_value = "0x000";
writeaddress_reset_value = "0x000";
length_reset_value = "0x000";
control_byte_reset_value = "0";
control_hw_reset_value = "0";
control_word_reset_value = "1";
control_doubleword_reset_value = "0";
control_quadword_reset_value = "0";
control_softwarereset_reset_value = "0";
control_go_reset_value = "0";
control_i_en_reset_value = "0";
control_reen_reset_value = "0";
control_ween_reset_value = "0";
control_leen_reset_value = "1";
control_rcon_reset_value = "0";
control_wcon_reset_value = "0";
lengthwidth = "13";
burst_enable = "0";
fifo_in_logic_elements = "1";
allow_byte_transactions = "1";
allow_hw_transactions = "1";
allow_word_transactions = "1";
allow_doubleword_transactions = "1";
allow_quadword_transactions = "1";
max_burst_size = "128";
big_endian = "0";
altera_show_unpublished_features = "0";
}
class = "altera_avalon_dma";
class_version = "7.07";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "pll_c0_out";
Has_Clock = "1";
Instantiate_In_System_Module = "1";
Top_Level_Ports_Are_Enumerated = "1";
View
{
MESSAGES
{
}
}
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/dma.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
SIMULATION
{
DISPLAY
{
SIGNAL aaa
{
format = "Logic";
name = "busy";
radix = "hexadecimal";
}
SIGNAL aab
{
format = "Logic";
name = "done";
radix = "hexadecimal";
}
SIGNAL aac
{
format = "Logic";
name = "length";
radix = "hexadecimal";
}
SIGNAL aad
{
format = "Logic";
name = "fifo_empty";
radix = "hexadecimal";
}
SIGNAL aae
{
format = "Logic";
name = "p1_fifo_full";
radix = "hexadecimal";
}
SIGNAL aaf
{
format = "Divider";
name = "dma read_master";
radix = "";
}
SIGNAL aag
{
format = "Literal";
name = "read_address";
radix = "hexadecimal";
}
SIGNAL aah
{
format = "Logic";
name = "read_chipselect";
radix = "hexadecimal";
}
SIGNAL aai
{
format = "Logic";
name = "read_endofpacket";
radix = "hexadecimal";
}
SIGNAL aaj
{
format = "Logic";
name = "read_flush";
radix = "hexadecimal";
}
SIGNAL aak
{
format = "Logic";
name = "read_read_n";
radix = "hexadecimal";
}
SIGNAL aal
{
format = "Literal";
name = "read_readdata";
radix = "hexadecimal";
}
SIGNAL aam
{
format = "Logic";
name = "read_readdatavalid";
radix = "hexadecimal";
}
SIGNAL aan
{
format = "Logic";
name = "read_waitrequest";
radix = "hexadecimal";
}
SIGNAL aao
{
format = "Divider";
name = "dma write_master";
radix = "";
}
SIGNAL aap
{
format = "Literal";
name = "write_address";
radix = "hexadecimal";
}
SIGNAL aaq
{
format = "Logic";
name = "write_byteenable";
radix = "hexadecimal";
}
SIGNAL aar
{
format = "Logic";
name = "write_chipselect";
radix = "hexadecimal";
}
SIGNAL aas
{
format = "Logic";
name = "write_endofpacket";
radix = "hexadecimal";
}
SIGNAL aat
{
format = "Logic";
name = "write_waitrequest";
radix = "hexadecimal";
}
SIGNAL aau
{
format = "Logic";
name = "write_write_n";
radix = "hexadecimal";
}
SIGNAL aav
{
format = "Literal";
name = "write_writedata";
radix = "hexadecimal";
}
}
}
}
}