| AUTO_WRITE_MASTER_CLOCKS_SAME |
0 |
| AUTO_WRITE_MASTER_INTERRUPT_USED_MASK |
-1 |
| AUTO_READ_MASTER_MAX_READ_LATENCY |
2 |
| AUTO_READ_MASTER_CLOCKS_SAME |
0 |
| AUTO_WRITE_MASTER_MAX_READ_LATENCY |
2 |
| AUTO_DEVICE_FAMILY |
STRATIXV |
| AUTO_ITL_CONTROL_CLOCKS_SAME |
0 |
| AUTO_READ_MASTER_INTERRUPT_USED_MASK |
-1 |
| AUTO_READ_MASTER_NEED_ADDR_WIDTH |
62 |
| AUTO_WRITE_MASTER_NEED_ADDR_WIDTH |
62 |
| PARAMETERISATION |
<interlacerParams><ITL_NAME>my_interlacing_core</ITL_NAME><ITL_MAX_WIDTH>1920</ITL_MAX_WIDTH><ITL_MAX_HEIGHT>1080</ITL_MAX_HEIGHT><ITL_BPS>10</ITL_BPS><ITL_CHANNELS_IN_SEQ>1</ITL_CHANNELS_IN_SEQ><ITL_CHANNELS_IN_PAR>2</ITL_CHANNELS_IN_PAR><ITL_FIRST_FIELD>FIELD_F0_FIRST</ITL_FIRST_FIELD><ITL_NO_BUFFERING>true</ITL_NO_BUFFERING><ITL_DROP_FRAMES>false</ITL_DROP_FRAMES><ITL_REPEAT_FIELDS>false</ITL_REPEAT_FIELDS><ITL_FRAMEBUFFERS_ADDR>00</ITL_FRAMEBUFFERS_ADDR><ITL_MEM_PORT_WIDTH>64</ITL_MEM_PORT_WIDTH><ITL_MEM_MASTERS_USE_SEPARATE_CLOCK>0</ITL_MEM_MASTERS_USE_SEPARATE_CLOCK><ITL_RDATA_FIFO_DEPTH>64</ITL_RDATA_FIFO_DEPTH><ITL_RDATA_BURST_TARGET>32</ITL_RDATA_BURST_TARGET><ITL_WDATA_FIFO_DEPTH>64</ITL_WDATA_FIFO_DEPTH><ITL_WDATA_BURST_TARGET>32</ITL_WDATA_BURST_TARGET><ITL_MAX_NUMBER_PACKETS>0</ITL_MAX_NUMBER_PACKETS><ITL_MAX_SYMBOLS_IN_PACKET>1</ITL_MAX_SYMBOLS_IN_PACKET><ITL_PROPAGATE_INTERLACED>false</ITL_PROPAGATE_INTERLACED><ITL_RUNTIME_CONTROL>true</ITL_RUNTIME_CONTROL><ITL_SYNC_SELECTION>0</ITL_SYNC_SELECTION></interlacerParams> |
| deviceFamily |
Stratix V |
| generateLegacySim |
false |