---

pll_0

altera_pll v12.1

Parameters device_family STRATIXV gui_device_speed_grade 2 gui_pll_mode Integer-N PLL fractional_vco_multiplier false gui_reference_clock_frequency 322.265625 reference_clock_frequency 322.265625 MHz gui_channel_spacing 0.0 gui_operation_mode normal gui_feedback_clock Global Clock gui_fractional_cout 24 pll_fractional_cout 32 gui_dsm_out_sel 1st_order pll_dsm_out_sel 1st_order operation_mode normal gui_use_locked true gui_en_adv_params false gui_number_of_clocks 1 number_of_clocks 1 gui_multiply_factor 1 gui_frac_multiply_factor 1 gui_divide_factor_n 1 gui_output_clock_frequency0 156.25 gui_divide_factor_c0 1 gui_actual_multiply_factor0 1 gui_actual_frac_multiply_factor0 1 gui_actual_divide_factor0 1 gui_actual_output_clock_frequency0 0 MHz gui_ps_units0 ps gui_phase_shift0 0 gui_phase_shift_deg0 0 gui_actual_phase_shift0 0 gui_duty_cycle0 50 gui_output_clock_frequency1 100.0 gui_divide_factor_c1 1 gui_actual_multiply_factor1 1 gui_actual_frac_multiply_factor1 1 gui_actual_divide_factor1 1 gui_actual_output_clock_frequency1 0 MHz gui_ps_units1 ps gui_phase_shift1 0 gui_phase_shift_deg1 0 gui_actual_phase_shift1 0 gui_duty_cycle1 50 gui_output_clock_frequency2 100.0 gui_divide_factor_c2 1 gui_actual_multiply_factor2 1 gui_actual_frac_multiply_factor2 1 gui_actual_divide_factor2 1 gui_actual_output_clock_frequency2 0 MHz gui_ps_units2 ps gui_phase_shift2 0 gui_phase_shift_deg2 0 gui_actual_phase_shift2 0 gui_duty_cycle2 50 gui_output_clock_frequency3 100.0 gui_divide_factor_c3 1 gui_actual_multiply_factor3 1 gui_actual_frac_multiply_factor3 1 gui_actual_divide_factor3 1 gui_actual_output_clock_frequency3 0 MHz gui_ps_units3 ps gui_phase_shift3 0 gui_phase_shift_deg3 0 gui_actual_phase_shift3 0 gui_duty_cycle3 50 gui_output_clock_frequency4 100.0 gui_divide_factor_c4 1 gui_actual_multiply_factor4 1 gui_actual_frac_multiply_factor4 1 gui_actual_divide_factor4 1 gui_actual_output_clock_frequency4 0 MHz gui_ps_units4 ps gui_phase_shift4 0 gui_phase_shift_deg4 0 gui_actual_phase_shift4 0 gui_duty_cycle4 50 gui_output_clock_frequency5 100.0 gui_divide_factor_c5 1 gui_actual_multiply_factor5 1 gui_actual_frac_multiply_factor5 1 gui_actual_divide_factor5 1 gui_actual_output_clock_frequency5 0 MHz gui_ps_units5 ps gui_phase_shift5 0 gui_phase_shift_deg5 0 gui_actual_phase_shift5 0 gui_duty_cycle5 50 gui_output_clock_frequency6 100.0 gui_divide_factor_c6 1 gui_actual_multiply_factor6 1 gui_actual_frac_multiply_factor6 1 gui_actual_divide_factor6 1 gui_actual_output_clock_frequency6 0 MHz gui_ps_units6 ps gui_phase_shift6 0 gui_phase_shift_deg6 0 gui_actual_phase_shift6 0 gui_duty_cycle6 50 gui_output_clock_frequency7 100.0 gui_divide_factor_c7 1 gui_actual_multiply_factor7 1 gui_actual_frac_multiply_factor7 1 gui_actual_divide_factor7 1 gui_actual_output_clock_frequency7 0 MHz gui_ps_units7 ps gui_phase_shift7 0 gui_phase_shift_deg7 0 gui_actual_phase_shift7 0 gui_duty_cycle7 50 gui_output_clock_frequency8 100.0 gui_divide_factor_c8 1 gui_actual_multiply_factor8 1 gui_actual_frac_multiply_factor8 1 gui_actual_divide_factor8 1 gui_actual_output_clock_frequency8 0 MHz gui_ps_units8 ps gui_phase_shift8 0 gui_phase_shift_deg8 0 gui_actual_phase_shift8 0 gui_duty_cycle8 50 gui_output_clock_frequency9 100.0 gui_divide_factor_c9 1 gui_actual_multiply_factor9 1 gui_actual_frac_multiply_factor9 1 gui_actual_divide_factor9 1 gui_actual_output_clock_frequency9 0 MHz gui_ps_units9 ps gui_phase_shift9 0 gui_phase_shift_deg9 0 gui_actual_phase_shift9 0 gui_duty_cycle9 50 gui_output_clock_frequency10 100.0 gui_divide_factor_c10 1 gui_actual_multiply_factor10 1 gui_actual_frac_multiply_factor10 1 gui_actual_divide_factor10 1 gui_actual_output_clock_frequency10 0 MHz gui_ps_units10 ps gui_phase_shift10 0 gui_phase_shift_deg10 0 gui_actual_phase_shift10 0 gui_duty_cycle10 50 gui_output_clock_frequency11 100.0 gui_divide_factor_c11 1 gui_actual_multiply_factor11 1 gui_actual_frac_multiply_factor11 1 gui_actual_divide_factor11 1 gui_actual_output_clock_frequency11 0 MHz gui_ps_units11 ps gui_phase_shift11 0 gui_phase_shift_deg11 0 gui_actual_phase_shift11 0 gui_duty_cycle11 50 gui_output_clock_frequency12 100.0 gui_divide_factor_c12 1 gui_actual_multiply_factor12 1 gui_actual_frac_multiply_factor12 1 gui_actual_divide_factor12 1 gui_actual_output_clock_frequency12 0 MHz gui_ps_units12 ps gui_phase_shift12 0 gui_phase_shift_deg12 0 gui_actual_phase_shift12 0 gui_duty_cycle12 50 gui_output_clock_frequency13 100.0 gui_divide_factor_c13 1 gui_actual_multiply_factor13 1 gui_actual_frac_multiply_factor13 1 gui_actual_divide_factor13 1 gui_actual_output_clock_frequency13 0 MHz gui_ps_units13 ps gui_phase_shift13 0 gui_phase_shift_deg13 0 gui_actual_phase_shift13 0 gui_duty_cycle13 50 gui_output_clock_frequency14 100.0 gui_divide_factor_c14 1 gui_actual_multiply_factor14 1 gui_actual_frac_multiply_factor14 1 gui_actual_divide_factor14 1 gui_actual_output_clock_frequency14 0 MHz gui_ps_units14 ps gui_phase_shift14 0 gui_phase_shift_deg14 0 gui_actual_phase_shift14 0 gui_duty_cycle14 50 gui_output_clock_frequency15 100.0 gui_divide_factor_c15 1 gui_actual_multiply_factor15 1 gui_actual_frac_multiply_factor15 1 gui_actual_divide_factor15 1 gui_actual_output_clock_frequency15 0 MHz gui_ps_units15 ps gui_phase_shift15 0 gui_phase_shift_deg15 0 gui_actual_phase_shift15 0 gui_duty_cycle15 50 gui_output_clock_frequency16 100.0 gui_divide_factor_c16 1 gui_actual_multiply_factor16 1 gui_actual_frac_multiply_factor16 1 gui_actual_divide_factor16 1 gui_actual_output_clock_frequency16 0 MHz gui_ps_units16 ps gui_phase_shift16 0 gui_phase_shift_deg16 0 gui_actual_phase_shift16 0 gui_duty_cycle16 50 gui_output_clock_frequency17 100.0 gui_divide_factor_c17 1 gui_actual_multiply_factor17 1 gui_actual_frac_multiply_factor17 1 gui_actual_divide_factor17 1 gui_actual_output_clock_frequency17 0 MHz gui_ps_units17 ps gui_phase_shift17 0 gui_phase_shift_deg17 0 gui_actual_phase_shift17 0 gui_duty_cycle17 50 output_clock_frequency0 156.25 MHz phase_shift0 0 ps duty_cycle0 50 output_clock_frequency1 0 MHz phase_shift1 0 ps duty_cycle1 50 output_clock_frequency2 0 MHz phase_shift2 0 ps duty_cycle2 50 output_clock_frequency3 0 MHz phase_shift3 0 ps duty_cycle3 50 output_clock_frequency4 0 MHz phase_shift4 0 ps duty_cycle4 50 output_clock_frequency5 0 MHz phase_shift5 0 ps duty_cycle5 50 output_clock_frequency6 0 MHz phase_shift6 0 ps duty_cycle6 50 output_clock_frequency7 0 MHz phase_shift7 0 ps duty_cycle7 50 output_clock_frequency8 0 MHz phase_shift8 0 ps duty_cycle8 50 output_clock_frequency9 0 MHz phase_shift9 0 ps duty_cycle9 50 output_clock_frequency10 0 MHz phase_shift10 0 ps duty_cycle10 50 output_clock_frequency11 0 MHz phase_shift11 0 ps duty_cycle11 50 output_clock_frequency12 0 MHz phase_shift12 0 ps duty_cycle12 50 output_clock_frequency13 0 MHz phase_shift13 0 ps duty_cycle13 50 output_clock_frequency14 0 MHz phase_shift14 0 ps duty_cycle14 50 output_clock_frequency15 0 MHz phase_shift15 0 ps duty_cycle15 50 output_clock_frequency16 0 MHz phase_shift16 0 ps duty_cycle16 50 output_clock_frequency17 0 MHz phase_shift17 0 ps duty_cycle17 50 gui_pll_auto_reset Off gui_pll_bandwidth_preset Auto gui_en_reconf false gui_en_dps_ports false gui_en_phout_ports false pll_type General pll_subtype General m_cnt_hi_div 1 m_cnt_lo_div 1 n_cnt_hi_div 1 n_cnt_lo_div 1 m_cnt_bypass_en true n_cnt_bypass_en true m_cnt_odd_div_duty_en false n_cnt_odd_div_duty_en false c_cnt_hi_div0 1 c_cnt_lo_div0 1 c_cnt_prst0 1 c_cnt_ph_mux_prst0 0 c_cnt_bypass_en0 true c_cnt_odd_div_duty_en0 false c_cnt_hi_div1 1 c_cnt_lo_div1 1 c_cnt_prst1 1 c_cnt_ph_mux_prst1 0 c_cnt_bypass_en1 true c_cnt_odd_div_duty_en1 false c_cnt_hi_div2 1 c_cnt_lo_div2 1 c_cnt_prst2 1 c_cnt_ph_mux_prst2 0 c_cnt_bypass_en2 true c_cnt_odd_div_duty_en2 false c_cnt_hi_div3 1 c_cnt_lo_div3 1 c_cnt_prst3 1 c_cnt_ph_mux_prst3 0 c_cnt_bypass_en3 true c_cnt_odd_div_duty_en3 false c_cnt_hi_div4 1 c_cnt_lo_div4 1 c_cnt_prst4 1 c_cnt_ph_mux_prst4 0 c_cnt_bypass_en4 true c_cnt_odd_div_duty_en4 false c_cnt_hi_div5 1 c_cnt_lo_div5 1 c_cnt_prst5 1 c_cnt_ph_mux_prst5 0 c_cnt_bypass_en5 true c_cnt_odd_div_duty_en5 false c_cnt_hi_div6 1 c_cnt_lo_div6 1 c_cnt_prst6 1 c_cnt_ph_mux_prst6 0 c_cnt_bypass_en6 true c_cnt_odd_div_duty_en6 false c_cnt_hi_div7 1 c_cnt_lo_div7 1 c_cnt_prst7 1 c_cnt_ph_mux_prst7 0 c_cnt_bypass_en7 true c_cnt_odd_div_duty_en7 false c_cnt_hi_div8 1 c_cnt_lo_div8 1 c_cnt_prst8 1 c_cnt_ph_mux_prst8 0 c_cnt_bypass_en8 true c_cnt_odd_div_duty_en8 false c_cnt_hi_div9 1 c_cnt_lo_div9 1 c_cnt_prst9 1 c_cnt_ph_mux_prst9 0 c_cnt_bypass_en9 true c_cnt_odd_div_duty_en9 false c_cnt_hi_div10 1 c_cnt_lo_div10 1 c_cnt_prst10 1 c_cnt_ph_mux_prst10 0 c_cnt_bypass_en10 true c_cnt_odd_div_duty_en10 false c_cnt_hi_div11 1 c_cnt_lo_div11 1 c_cnt_prst11 1 c_cnt_ph_mux_prst11 0 c_cnt_bypass_en11 true c_cnt_odd_div_duty_en11 false c_cnt_hi_div12 1 c_cnt_lo_div12 1 c_cnt_prst12 1 c_cnt_ph_mux_prst12 0 c_cnt_bypass_en12 true c_cnt_odd_div_duty_en12 false c_cnt_hi_div13 1 c_cnt_lo_div13 1 c_cnt_prst13 1 c_cnt_ph_mux_prst13 0 c_cnt_bypass_en13 true c_cnt_odd_div_duty_en13 false c_cnt_hi_div14 1 c_cnt_lo_div14 1 c_cnt_prst14 1 c_cnt_ph_mux_prst14 0 c_cnt_bypass_en14 true c_cnt_odd_div_duty_en14 false c_cnt_hi_div15 1 c_cnt_lo_div15 1 c_cnt_prst15 1 c_cnt_ph_mux_prst15 0 c_cnt_bypass_en15 true c_cnt_odd_div_duty_en15 false c_cnt_hi_div16 1 c_cnt_lo_div16 1 c_cnt_prst16 1 c_cnt_ph_mux_prst16 0 c_cnt_bypass_en16 true c_cnt_odd_div_duty_en16 false c_cnt_hi_div17 1 c_cnt_lo_div17 1 c_cnt_prst17 1 c_cnt_ph_mux_prst17 0 c_cnt_bypass_en17 true c_cnt_odd_div_duty_en17 false pll_vco_div 1 pll_cp_current 5 pll_bwctrl 18000 pll_output_clk_frequency 0 MHz pll_fractional_division 1 mimic_fbclk_type gclk pll_fbclk_mux_1 glb pll_fbclk_mux_2 fb_1 pll_m_cnt_in_src ph_mux_clk gui_parameter_list gui_parameter_values gui_mif_generate false gui_enable_mif_dps false gui_dps_cntr C0 gui_dps_num 1 gui_dps_dir Positive gui_refclk_switch false gui_refclk1_frequency 100.0 gui_switchover_mode Automatic Switchover gui_switchover_delay 0 gui_active_clk false gui_clk_bad false refclk1_frequency 100.0 MHz pll_clk_loss_sw_en false pll_manu_clk_sw_en false pll_auto_clk_sw_en false pll_clkin_1_src clk_0 pll_clk_sw_dly 0 gui_enable_cascade_out false gui_enable_cascade_in false pll_clkin_0_src clk_0 gui_pll_cascading_mode Create an adjpllin signal to connect with an upstream PLL AUTO_REFCLK_CLOCK_RATE 322265625 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

mm_clk

clock_source v12.1

Parameters clockFrequency 1000000000 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

ref_clk_10g

clock_source v12.1

Parameters clockFrequency 322265625 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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ref_clk_1g

clock_source v12.1

Parameters clockFrequency 125000000 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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merlin_master_translator_0

altera_merlin_master_translator v12.1

Parameters AV_ADDRESS_W 20 AV_DATA_W 32 AV_BURSTCOUNT_W 4 AV_BYTEENABLE_W 4 UAV_ADDRESS_W 32 UAV_BURSTCOUNT_W 3 AV_READLATENCY 0 AV_WRITE_WAIT 0 AV_READ_WAIT 0 AV_DATA_HOLD 0 AV_SETUP_WAIT 0 USE_READDATA 1 USE_WRITEDATA 1 USE_READ 1 USE_WRITE 1 USE_BEGINBURSTTRANSFER 0 USE_BEGINTRANSFER 0 USE_BYTEENABLE 0 USE_CHIPSELECT 0 USE_ADDRESS 1 USE_BURSTCOUNT 0 USE_DEBUGACCESS 0 USE_CLKEN 0 USE_READDATAVALID 0 USE_WAITREQUEST 1 USE_LOCK 0 AV_SYMBOLS_PER_WORD 4 AV_ADDRESS_SYMBOLS 1 AV_BURSTCOUNT_SYMBOLS 1 AV_CONSTANT_BURST_BEHAVIOR 0 UAV_CONSTANT_BURST_BEHAVIOR 0 AV_LINEWRAPBURSTS 0 AV_MAX_PENDING_READ_TRANSACTIONS 0 AV_BURSTBOUNDARIES 0 AV_INTERLEAVEBURSTS 0 AV_BITS_PER_SYMBOL 8 AV_ISBIGENDIAN 0 AV_ADDRESSGROUP 0 UAV_ADDRESSGROUP 0 AV_REGISTEROUTGOINGSIGNALS 0 AV_REGISTERINCOMINGSIGNALS 0 AV_ALWAYSBURSTMAXBURST 0 AUTO_CLK_CLOCK_RATE 1000000000 AUTO_DEVICE_FAMILY STRATIXV deviceFamily Stratix V generateLegacySim false

  

Software Assignments (none)

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pll_outclk

clock_source v12.1

Parameters clockFrequency 156250000 clockFrequencyKnown true inputClockFrequency 156250000 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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clk_0

clock_source v12.1

Parameters clockFrequency 156250000 clockFrequencyKnown true inputClockFrequency 156250000 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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xcvr_reset_control_2

altera_xcvr_reset_control v12.1

Parameters CHANNELS 1 PLLS 1 SYS_CLK_IN_MHZ 100 SYNCHRONIZE_RESET 1 REDUCED_SIM_TIME 1 gui_split_interfaces 0 TX_PLL_ENABLE 1 T_PLL_POWERDOWN 1000 SYNCHRONIZE_PLL_RESET 0 TX_ENABLE 1 TX_PER_CHANNEL 0 gui_tx_auto_reset 1 T_TX_DIGITALRESET 20 T_PLL_LOCK_HYST 0 RX_ENABLE 1 RX_PER_CHANNEL 0 gui_rx_auto_reset 0 T_RX_ANALOGRESET 40 T_RX_DIGITALRESET 4000 l_terminate_pll 0 l_terminate_tx 0 l_terminate_rx 0 l_terminate_tx_manual 1 l_terminate_rx_manual 1 l_tx_manual_term 1 l_rx_manual_term 0 l_pll_select_split 0 l_pll_select_width 1 l_pll_select_base 1 AUTO_CLOCK_CLOCK_RATE 1000000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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xcvr_10gbase_kr_2

altera_xcvr_10gbase_kr v12.1

Parameters DEVICE_FAMILY STRATIXV sel_backplane_lineside 1Gb/10Gb Ethernet chk_backplane 0 SYNTH_AN 0 SYNTH_LT 0 SYNTH_SEQ 1 SYNTH_GIGE 1 SYNTH_GMII_gui 1 SYNTH_GMII 1 SYNTH_SGMII 1 SYNTH_1588_1G 0 PHY_IDENTIFIER 0 DEV_VERSION 0 SYNTH_CL37ANEG 1 REF_CLK_FREQ_1G 125.00 MHz PLL_TYPE_1G CMU phy_mgmt_clk_freq_valid 1 phy_mgmt_clk_freq 125.00 LINK_TIMER_KR_valid 1 LINK_TIMER_KR 504.00 LINK_TIMER_KX_valid 1 LINK_TIMER_KX 48.00 LFT_R_MSB 63 LFT_R_LSB 0 LFT_X_MSB 6 LFT_X_LSB 0 OPTIONAL_DM 0 OPTIONAL_UP 0 BERWIDTH_gui 15 BERWIDTH 4 TRNWTWIDTH_gui 127 TRNWTWIDTH 7 MAINTAPWIDTH 6 POSTTAPWIDTH 5 PRETAPWIDTH 4 VMAXRULE 60 VMINRULE 9 VODMINRULE 22 VPOSTRULE 25 VPRERULE 15 PREMAINVAL 60 PREPOSTVAL 0 PREPREVAL 0 INITMAINVAL 35 INITPOSTVAL 14 INITPREVAL 3 AN_GIGE 1 AN_XAUI 0 AN_BASER 1 AN_40GBP 0 AN_40GCR 0 AN_100G 0 AN_PAUSE 0 AN_PAUSE_C0 0 AN_PAUSE_C1 0 AN_TECH 5 AN_FEC 0 AN_SELECTOR 1 PLL_CNT 2 SYNTH_1588_10G 0 REF_CLK_FREQ_10G 322.265625 MHz PLL_TYPE_10G ATX OPTIONAL_10G 1 OPTIONAL_10G_RCVD 1 OPTIONAL_PLL_LCK 1 l_rcfg_interfaces 3 l_rcfg_to_xcvr_width 210 l_rcfg_from_xcvr_width 138 AUTO_PLL_REF_CLK_10G_CLOCK_RATE 322265625 AUTO_PLL_REF_CLK_1G_CLOCK_RATE 125000000 AUTO_XGMII_TX_CLK_CLOCK_RATE 156250000 AUTO_XGMII_RX_CLK_CLOCK_RATE 156250000 AUTO_TX_CORECLKIN_1G_CLOCK_RATE 0 AUTO_RX_CORECLKIN_1G_CLOCK_RATE 0 AUTO_MGMT_CLK_CLOCK_RATE 1000000000 AUTO_CALC_CLK_1G_CLOCK_RATE -1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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eth_10g_design_example_2

altera_eth_10g_design_example v12.1

Parameters DEVICE_FAMILY_TOP STRATIXV ENABLE_MAC_LOOPBACK 10Gbps Ethernet MAC with LoopBack Enabled CHOOSE_MDIO_2_WIRE_SERIAL_INT 1 PHY_IP 2 CHOOSE_FIFO 0 ENABLE_TIMESTAMPING 0 ENABLE_PTP_1STEP 0 TSTAMP_FP_WIDTH 4 PREAMBLE_PASSTHROUGH 0 ENABLE_PFC 0 PFC_PRIORITY_NUM 8 DATAPATH_OPTION 3 ENABLE_SUPP_ADDR 1 INSTANTIATE_TX_CRC 1 INSTANTIATE_STATISTICS 1 REGISTER_BASED_STATISTICS 0 ENABLE_1G10G_MAC 1 MDIO_MDC_DIVISOR 32 SYNC_TX_FIFO_SYMBOLS_PER_BEAT 8 SYNC_TX_FIFO_BITS_PER_SYMBOL 8 SYNC_TX_FIFO_DEPTH 512 SYNC_TX_FIFO_ERROR_WIDTH 1 SYNC_TX_USE_PACKETS 1 SYNC_TX_USE_FILL 1 SYNC_TX_USE_STORE_AND_FORWARD 1 SYNC_TX_USE_ALMOST_FULL 0 SYNC_TX_USE_ALMOST_EMPTY 0 SYNC_RX_FIFO_SYMBOLS_PER_BEAT 8 SYNC_RX_FIFO_BITS_PER_SYMBOL 8 SYNC_RX_FIFO_DEPTH 512 SYNC_RX_FIFO_ERROR_WIDTH 6 SYNC_RX_USE_PACKETS 1 SYNC_RX_USE_FILL 1 SYNC_RX_USE_STORE_AND_FORWARD 1 SYNC_RX_USE_ALMOST_FULL 1 SYNC_RX_USE_ALMOST_EMPTY 1 ASYNC_TX_FIFO_SYMBOLS_PER_BEAT 8 ASYNC_TX_FIFO_BITS_PER_SYMBOL 8 ASYNC_TX_FIFO_DEPTH 16 ASYNC_TX_FIFO_ERROR_WIDTH 1 ASYNC_TX_USE_PKT 1 ASYNC_TX_USE_SINK_FILL 0 ASYNC_TX_USE_SRC_FILL 0 ASYNC_RX_FIFO_SYMBOLS_PER_BEAT 8 ASYNC_RX_FIFO_BITS_PER_SYMBOL 8 ASYNC_RX_FIFO_DEPTH 16 ASYNC_RX_FIFO_ERROR_WIDTH 6 ASYNC_RX_USE_PKT 1 ASYNC_RX_USE_SINK_FILL 0 ASYNC_RX_USE_SRC_FILL 0 BASER_INTERFACE 0 BASER_PLL_TYPE CMU BASER_STARTING_CHANNEL_NUMBER 0 BASER_REF_CLK_FREQ 644.53125 MHz BASER_TRANSMITTER_TERMINATION OCT_100_OHMS BASER_PRE_EMPHASIS_PRE_TAP 0 BASER_PRE_EMPHASIS_PRE_TAP_POLARITY 0 BASER_PRE_EMPHASIS_FIRST_POST_TAP 5 BASER_PRE_EMPHASIS_SECOND_POST_TAP 0 BASER_PRE_EMPHASIS_SECOND_POST_TAP_POLARITY 0 BASER_TRANSMITTER_VOD 1 BASER_RECEIVER_TERMINATION OCT_100_OHMS BASER_RECEIVER_DC_GAIN 0 BASER_RECEIVER_STATIC_EQUALIZER 14 BASER_EXT_PMA_CONTROL_CONF 0 BASER_ENA_ADD_CONTROL_STAT 0 BASER_RECOVERED_CLK_OUT 0 XAUI_STARTING_CHANNEL_NUMBER 0 starting_channel_number 0 interface_type Soft XAUI soft_xaui_cfg Only Soft XAUI is supported for this device. hard_xaui_cfg Only Hard XAUI is supported for this device. data_rate 3125 Mbps xaui_pll_type AUTO gui_pll_type CMU GUI_BASE_DATA_RATE BASE_DATA_RATE use_control_and_status_ports 0 external_pma_ctrl_reconf 0 recovered_clk_out 0 number_of_interfaces 1 reconfig_interfaces 1 use_rx_rate_match 0 tx_termination OCT_100_OHMS tx_vod_selection 4 tx_preemp_pretap 0 tx_preemp_pretap_inv 0 tx_preemp_tap_1 0 tx_preemp_tap_2 0 tx_preemp_tap_2_inv 0 rx_common_mode 0.82v rx_termination OCT_100_OHMS rx_eq_dc_gain 0 rx_eq_ctrl 0 AUTO_DEVICE 5SGXEA7N2F40C2 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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reset_controller_mac_rx_2

altera_reset_controller v12.1

Parameters NUM_RESET_INPUTS 2 OUTPUT_RESET_SYNC_EDGES deassert SYNC_DEPTH 2 AUTO_CLK_CLOCK_RATE 322265625 AUTO_DEVICE_FAMILY STRATIXV deviceFamily Stratix V generateLegacySim false

  

Software Assignments (none)

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reset_controller_mac_tx_2

altera_reset_controller v12.1

Parameters NUM_RESET_INPUTS 2 OUTPUT_RESET_SYNC_EDGES deassert SYNC_DEPTH 2 AUTO_CLK_CLOCK_RATE 322265625 AUTO_DEVICE_FAMILY STRATIXV deviceFamily Stratix V generateLegacySim false

  

Software Assignments (none)

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reset_controller_2

altera_reset_controller v12.1

Parameters NUM_RESET_INPUTS 2 OUTPUT_RESET_SYNC_EDGES deassert SYNC_DEPTH 2 AUTO_CLK_CLOCK_RATE 156250000 AUTO_DEVICE_FAMILY STRATIXV deviceFamily Stratix V generateLegacySim false

  

Software Assignments (none)