Soft rate match FIFO

Soft rate match FIFO

Design Specifications

The table below lists the specifications for this design:

Attribute	Specification
Device Family	Cyclone IV GX
FPGA	Not Specific
Quartus Version	13.0
Modelsim Version	Modelsim SE v6.6d
Data rate	1.25Gbps
Data Pattern	From Spirent Tester or User self generated
Number of Channel	1
IP used	ALTGX Basic, Transceiver Reconfiguration Controller

Design Objective

In transceiver Basic mode, Rate match FIFO is used to compensate the clock frequency difference between local CDR recovered clock and upstream transmitter clock by insert and delete the special rate match characters.Rate match FIFO can compensate for small clock frequency up to +/- 300PPM.

Mostly of the users thought that the hard rate match FIFO's deletion/insertion method for Transceiver Basic mode is same as Transceiver GIGE mode. However, this is totally wrong because in Basic mode, the deletion/insertion was based on /K-S/ ordered set. A /K-S/ ordered set is defined as a /K/ followed by a consecutive number of /S/ (KSSS).The symbols inserted/deleted are /S/ only.Besides that, when rate match FIFO's full signal was asserted, the rate match FIFO will automatic delete the data byte that cause the FIFO to go full. For further info on how transceiver rate match FIFO perform deletion/insertion in Basic mode, please refer to Altera Device Handbook Vol.2, Transceiver Functional Modes chapter.

Below diagram show how the deletion,insertion,FIFO full condition happen in Basic mode.

1/1b/Deletion.jpg

7/75/Insertion.jpg

a/a6/Full.jpg

This problem can be replicated via controlling the clock difference between TX and RX side as shown in diagram below.

5/5e/Setup.jpg

Both dev kit's reference clock is synchronized.This will ease for control the PPM difference between local CDR recovered clock and upstream transmitter clock. The pattern sequence been used is …IPG->DATA->IPG->DATA…, Where IPG= BC50, DATA=55AA. By just increased 10PPM at TX side, we can observe the result via SignalTap. Capture the signal at the RX through SignalTap.

4/47/Result.jpg

Design Overview

Soft Rate Match FIFO Design

3/3c/Design.jpg

User need to design a soft RM FIFO that will able to perform full |C2| (BC420000) character deletion during AN process and deletion/insertion of |I2| character during inter-packet gap.

High-level description:

A soft RM FIFO will implement at core logic side and perform the insertion/deletion of |C2| / |I2| character if the PPM threshold is over.
A serializer/de-serializer block need to be constructed before/after soft RM FIFO block.

There is a need of data-width conversion from 16-bit to 8-bit because soft RM FIFO is 8- bit data width while RX transceiver is 16-bit dataout.

Soft Rate Match FIFO Architecture

2/2b/Design_1.jpg

Flip-flop is used for |C2| (BC42) and |I2| (BC50) character detect.
RM FIFO write (deletion) is clocked by recovered clock while RM FIFO read (insertion) of character is based on tx_clkout.
Deletion happen when FIFO is full and detection of |C2|(BC42) / |I2| (BC50) character pattern was found.
User should stop write into the FIFO at this moment. Number of cycle of stop write is depend on the number of byte of |C2|(BC420000) / |I2| (BC50).
Same condition applied for insertion happen. Insertion happen when FIFO is over the empty condition threshold value and detection the |C2| (BC42) / |I2| (BC50) character pattern was found.
User should stop read from FIFO. Number of cycle of stop read is depend on the number of byte of |C2| (BC420000) / |I2| (BC50).
User need to determine the FIFO depth accordingly to their system design.

Rate Match FIFO Depth Calculation

Data packet size – (data packet size x (1 Million +/- PPM )/1 Million) = offset

Can be applied to calculate the frequency range.

For example

2 counter using different clock source

PPM = +/- 400 PPM

Data packet size = 10K byte (etc: Jumbo frame)

Calculation:

10K – (10K x (1Million +/- 400)/1 Million) = +/- 4

Design File Link

Soft Rate Match FIFO File (ZIP)

External Link

aiigx_5v1.pdf

aiigx_5v3.pdf

Key Words

Cyclone IV, ALTGX Basic, Rate Match FIFO, IEEE 802.3 Clause 37 1000BASE-X Auto-Negotiation, SGMII Auto-Negotiation

supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable,

misleading or inaccurate.