Success! Subscription added.
Success! Subscription removed.
Sorry, you must verify to complete this action. Please click the verification link in your email. You may re-send via your profile.
This document describes various tips for using Incremental Compilation and LogicLock.
File:Tips for IncrementalCompilation LogicLock.pdf
Here is the Table of Contents for reference:
Table of Contents
Introduction 3
Timing Analysis 3
Tip – Analyze paths from/to the source and destination of critical path 4
Tip – Locate multiple paths to the Chip Planner 6
Tip – Create a .tcl script to monitor critical paths across compiles 7
Incremental Compilation and LogicLock – Brief Overview 7
Tip – Monitor area and slack differences when adding partitions 8
Tip – Optimize Screen Space for LogicLock and Design Partition Windows 8
Basic Incremental Compilation Tips 9
Tip: Quick Block Stitch with Partitions 9
Tip: Create a Black-Box for Incomplete or Invalid Logic 11
Tip: Put Non-Altera IP into Empty Partition 12
Tip: Create Empty Partitions to Save Space 12
Tip: Put Hierarchy Being Modified into a Partition for Quick Compiles 13
Tip: Set the Top level partition to Post-fit when using SignalTap 13
Tip: Partition I/O Interfaces 14
Incremental Compilation for Isolating Hierarchies 14
Tip: Get as Much Margin as Possible When Designing Blocks 15
Tip: Hierarchy Isolation Method 1 - Set Partition Top to Empty 16
Tip: Hierarchy Isolation Method 2 - Set Adjacent Partitions to Empty 17
Incremental Compilation for Performance 18
Tip: When Preserving Performance of a Partition, Create a .qxp 19
Tip: Incremental Compilation for Performance Method 1: Building Up a Design 20
Tip: Incremental Compilation for Performance Method 2: Isolating Multiple Partitions 21
Tip: LogicLock when Preserving Performance with Incremental Compilation? 22
Floorplanning with LogicLock Regions 23
Tip: Floorplanning I/O Interfaces 24
Tip: Floorplan for Incremental Compilation on a Single Hierarchy 25
Floorplanning the Entire Design for Incremental Compilation 26
Tip: Do not create too many Design Partitions or LogicLock Regions 27
Tip: Avoid over-using Floating or Auto-Sized LogicLock regions 27
Tip: Right-Click Locate Hierarchies from Project Navigator to Chip Planner 28
Floorplannining for Performance 29
Low-Level Floorplanning 29
Tip: Putting critical paths in a LogicLock Region usually does not improve timing 29
Tip: Over-Constraining 30
High-Level Floorplanning 31
Tip: Think Up-Front If Design Can Be Floorplanned 31
Tip: Use Block Diagram 33
Tip: Analyze the Unfloorplanned Fit 33
Tip: Keep It Simple 35
Tip: Over Floorplan when Obvious 36
Tip: Floorplan to Break Timing 37
Tip: Add set_false_path to Test How Potential Modifications Effect Overall Fit 38
Conclusion 39
Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.
Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.
For more complete information about compiler optimizations, see our Optimization Notice.