Transceiver Design Flow

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Transceiver Design Flow

Overview

This series of articles guides the reader through the steps required to design, compile, simulate, and port to hardware any transceiver design using a Stratix V FPGA from scratch.

• Level 1 Design Flow  - A walkthrough for the creation of a Native PHY IP reference design. Essentially a high-level view of the steps a designer would take in order to create, compile, simulate, and HW checkout a Physical Layer design for a Stratix V supported communication protocol. Users who are new to transceivers, new to Altera generated IP, or would just like a refresher course in creating a design should view this article before proceeding to create a transceiver design. Level 1 explains "what" to do in order to make a transceiver design.
• Level 2 Design Flow - provides technical details about the steps taken in the Level 1 article. Users who require extra guidance besides that found in the PHY IP Core User Guide should view the Level 2 Articles. Level 2 articles explain "why" the steps in Level 1 were taken.
• Level 3 Design Flow - are geared towards teaching the user to design a transceiver on their own. If Level 1 articles are the "What", and Level 2 articles are the "Why", then Level 3 articles are the "How." Examples may include writing .Tcl scripts for ModelSim Compilation, Using a Microprocessor as an Avalon MM Master, or even How to use an Oscilloscope with a Stratix V SI Development kit.

Required Materials

• Quartus II 12.0 (preferably the latest official release) - and basic knowledge of its use.
• Modelsim 10.0d - and basic knowledge of its use.
• Stratix V device and SI Board

Documentation

• Intel® Stratix® Documentation - Use this for information on Stratix V device architecture.
• Transceiver Configurations in Stratix V Devices - Provides the transceiver channel datapath, clocking guidelines, channel placement guidelines, and a brief description of protocol features supported in each transceiver configuration for Stratix V devices.
• Altera Transceiver PHY IP Core User Guide    - Provides a general overview of the Altera IP core design flow to help you quickly get started with any Altera PHY IP core. The Altera IP Library is installed as part of
• the Quartus II installation process. You can select and parameterize any Altera IP core from the library using the MegaWizard in Quartus II.
• Avalon Specification - This document defines interfaces appropriate for streaming high-speed data, reading and writing registers and memory, and controlling off-chip devices.

Supported Protocols

Stratix V devices have a dedicated transceiver physical coding sublayer (PCS) and physical medium attachment (PMA) circuitry, and a dedicated PHY IP to support the following communication protocols: 

Protocol	PHY IP	Documentation
10G-BaseR	10GBase-R PHY v12.0	Transceiver Configurations in Stratix V Devices and Altera Transceiver PHY IP Core User Guide
XAUI	XAUI PHY v12.0	Transceiver Configurations in Stratix V Devices and Altera Transceiver PHY IP Core User Guide
Interlaken	Interlaken PHY v12.0	Transceiver Configurations in Stratix V Devices and Altera Transceiver PHY IP Core User Guide
PCI Express	PIPE v12.0 or Hard IP v12.0	Transceiver Configurations in Stratix V Devices and Altera Transceiver PHY IP Core User Guide
SDC	Custom PHY IP	Transceiver Configurations in Stratix V Devices and Altera Transceiver PHY IP Core User Guide
SDI	Custom PHY IP	Transceiver Configurations in Stratix V Devices and Altera Transceiver PHY IP Core User Guide
Ethernet	Custom PHY IP	Transceiver Configurations in Stratix V Devices and Altera Transceiver PHY IP Core User Guide
Serial RapidIO	Custom PHY IP	Transceiver Configurations in Stratix V Devices and Altera Transceiver PHY IP Core User Guide
Serial ATA, SAS	Custom PHY IP	Transceiver Configurations in Stratix V Devices and Altera Transceiver PHY IP Core User Guide
GPON	Custom PHY IP	Transceiver Configurations in Stratix V Devices and Altera Transceiver PHY IP Core User Guide
Serial RapidIO	Custom PHY IP	Transceiver Configurations in Stratix V Devices and Altera Transceiver PHY IP Core User Guide
Others...	Custom PHY IP	Transceiver Configurations in Stratix V Devices and Altera Transceiver PHY IP Core User Guide
CIPRI	Deterministic Latency PHY IP	Transceiver Configurations in Stratix V Devices and Altera Transceiver PHY IP Core User Guide and Implementing CIPRI
OBSAI	Deterministic Latency PHY IP	Transceiver Configurations in Stratix V Devices and Altera Transceiver PHY IP Core User Guide
1588 Ethernet	Deterministic Latency PHY IP	Transceiver Configurations in Stratix V Devices and Altera Transceiver PHY IP Core User Guide
PMA only	Native PHY IP	Transceiver Configurations in Stratix V Devices and Altera Transceiver PHY IP Core User Guide

Articles

• Level 1 - Basic Guide to Creating a Transceiver Design
• Level 2 - The Reconfiguration Controller
• Level 2 - The Reset Controller
• Level 2 - The Transceiver PHY IP
• Level 2 - The Avalon MM Master
• Level 2 - Writing a Compilation .Tcl for ModelSim

Key Words

Stratix V, PCIE PIPE PHY IP, Tranceiver Reconfiguration Controller, Physical layer, PCI Express, Express, Stratix Five, GT, GS, GX, Design, Example, guide, walkthrough,

PCIe, PCI E, PCI Express, Stratix V, SV, S, V, Walkthrough, guide, help, Stratix V GX, Stratix V GT, SV, SVGX, SVGT, S5GX, S5GT, S5, Stratix 5, Stratix 5 GX, StratixV, StratixV GX, Stratix5, Stratix5 GX, Altera, generated, generation, Instantiation, creation, design, files,transceiver, design, flow

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