Triple Speed Ethernet Debug Checklist

Triple Speed Ethernet Debug Checklist

Last Major Update

March 4, 2015

Introduction

This wiki page provides debug checklist and guidance for Altera® Triple-Speed Ethernet (TSE) MegaCore® function. It serves as a reference for TSE IP user during issue debugging.

Debug Checklist

1. Sanity check on design.

• Signal connectivity check (e.g. via RTL/Technology Map Viewer).

• Clock frequency check (e.g. via Fitter/TimeQuest Timing report).

• Timing constraint and violation check (e.g. via Timing Analysis log message/ TimeQuest Timing report).

• Board connectivity check.

2. Search in altera.com for similar failures of the IP.

3. Check register settings for the IP.

4. Identify failing area (e.g. MAC loopback/PHY loopback/TX data/RX data).

Avalon ST Case Study

1. Make sure Avalon ST interface behavior follow the spec.

d/d4/AvalonST.png

2. Identify unexpected behavior.

a/a7/Avalon-ST-CS.png

3. Check FIFO status ( if possible) : almost full/almost empty.

a/a7/Avalon-ST-CS.png

4. SignalTap Avalon ST FIFO and State Machine.

• Add Avalon ST FIFO nodes (e.g. *altera_tse_a_fifo_opt_1246:RXDATA* and *altera_tse_a_fifo_opt_1246:TXDATA*) to SignalTap II.

2/24/AvalonST-HowToSignalTap.png

• Add Avalon ST FIFO State Machine (e.g. *altera_tse_rx_min_ff:U_RXFF|state* and *altera_tse_rx_min_ff:U_TXFF|state*) to SignalTap II. 7/7c/AddSMNodeST1.png

5. The issue is caused by Avalon ST RX FIFO Almost Empty is not configured properly (0000h). Please take note on the FIFO status, FIFO full is detected in this case. 6/63/AddSMNodeST2.png

Statistic Counter Case Study

Statistic counters count the packet at GMII interface, not at Avalon ST interface. For hardware, add all GMII if signals to signal tap to observe the transmitted, received or error packets. For simulation, if the TSE variants are not MAC only, GMII are internal signals which can’t be seen. In that case, observe led_crs to confirm the packet being transmitted or received.

Example: 10 packets are sent at the parallel port of the tx side and 4 of these packets are erroneous (tx_error='1'). However, the value that I get from the aFramesTransmittedOK register is 5 instead of 6.

h4/4e/Simwave.png

c/cb/Simwave2.png

Packet Drop Case Study

Example: MAC drop packet at TX (packet is observed at Avalon ST IF, but not at MII/GMIII/RGMII IF) & RX (packet is observed at MII/GMII/RGMII IF but not at Avalon ST IF).

1. Read command_config register and make sure that MAC TX_ENA and RX_ENA bit are set to 1.

2. Make sure MAC is not in SW reset state.

3. For Rx path, make sure MII/GMII/RGMII packets are correct Ethernet format.

8/80/CS3.png

Congestion & Flow Control Case Study

When MAC receives an XOFF frame, it will complete the transfer of the current frame and stop transmission for the amount of time specified by the pause quanta in 512 bit (64 bytes) times increments.

e.g. Pause quanta = 2 , GMII IF

8 bit times = 1 clock cycle → 512 bit times = 64 clock cycles

Pause Quanta time = 2 x64 clock cycles = 128 clock cycles

Transmission resumes when timer (pause quanta time) expires or MAC function received an XON frame. Holdoff Quanta specifies the gap between consecutive XOFF requests in 512 bit times increments.

When “Enable full-duplex flow control” option turn on, pause frame is triggered by:

• RX FIFO : rx_section_empty

• Register: XON/XOFF reg

• I/O pin : xon_gen / xoff_gen

f/f4/PFformat.png

Pause Frame:

• src addr=mac_0 and mac_1

• dest addr =01-80-C2-00-00-01

• Pad = 42 bytes of 0x00

XOFF: [P1,P2] = value[pause_quant reg]

XON: [P1,P2] = 0x0000

f/f3/PFsimwave.png

To investigate on congestion and flow control related issue,

1. Make sure Flow control feature in GUI is enable.

• If this feature is not enable, all the thing functions related to Flow Control such as Pause_fwd, Pause_ignore, Xon,Xoff generation will be disable too

2. Check Flow Control Configuration Setting.

• pause_quant register

• holdoff_quant register

• command_config register: XON_GEN, XOFF_GEN, PAUSE_FWD, PAUSE_IGNORE

3. Identify Pause Frame trigger condition.

4. Identify Pause Quanta & HoldOff Quata time.

• For TX: Set Pause Quanta time by configure the register

• For RX: Check the Pause Quanta field in the received packet

5. Check Pause Frame Format Packet.

6. Make sure the simulation time is enough.

• At least more than Pause Quanta time

b/b4/PFsimwave2.png

Figure 12 shows simulation waveform for a case where MAC stopped transmit packet after receiving XOFF frame. This is because Pause Quanta value is set to 0x0100 instead of 0x0001 and the simulation time not enough to cover the pause quanta time.

Loopback Case Study

Loopback mode:

• Ethernet loopback (at MII/GMII)

• Serial loopback (at PMA) not support in Cyclone IV and V series Devices until Quartus® II v13.0

Use the same clock source for both transmit and receive clocks. If you use different clock sources, ensure that the difference between the transmit and receive clocks is less than ±100 ppm.

Link Synchronization Case Study

Link synchronization – ensure CDR is stable and word alignment

Ethernet can achieve link if received 3 comma characters

• /Idle/ character – Inter-packet-gap

Example waveform on transceiver interface (8bits data):

8/8b/Idlec.png

• /C1/ and /C2/ character – Configuration for Auto Negotiation

Example waveform on transceiver interface (8bits data):

f/f3/C12c.png

To investigate on link synchronization issue,

1. Check the Transceiver/LVDS interface to make sure pll is locked and rxfreq_lock/rxlock_todata/rx_lock_to_ref are asserted.

2. Check all resets included reset sequence to make sure core is out of reset.

3. Signal tap Link State Machine and 8 bit interface data as output of 8b/10b decoder.

• Use the keywords as shown in Figure 13 to find 8b/10b decoder and encoder nodes

e/ef/8b10bst.png

• Use the keywords as shown in Figure 14 to find state machine nodes

1/14/Smst.png

Transceiver is not encrypted in the TSE IP library (clear text RTL is provided), use the keywords

• altera_tse_gxb_gige_inst (IV Series devices and below)

• altera_tse_gxb_gige_phyip_inst (V series devices)

2/27/Tst.png

Example: Ethernet link down intermittently.

1. Check the link and AN status:

• LED_LINK and LED_AN output from the TSE IP

• PCS Status Register bit 2 for link status and bit 5 for AN Complete

2. Check the transmit and receive data.

1/1d/CsLink1.png

Root Cause: The TSE reset sequencer keep asserting the rx_digitalreset forever

8/87/CsLink2.png

d/db/CsLink3.png

Auto Negotiation Case Study

To investigate on Auto Negotiation related issue,

1. Make sure link synchronization is up.

2. Check the Auto Negotiation configuration setting.

• Enable SGMII Auto Negotiation in MAC mode and PHY mode.

• Enable 1000 Base X AN.

• Set Link Timer .

• Set Device Ability for 1000 Base-X Auto Negotiation.

3. Check simulation time >4x Link timer.

4. SignalTap 8bit interface (same as Link issue).

5. Check where Auto Negotiation progress stop.

6. Identify the conditions which cause Auto Negotiation stop.

• Analyze dev_ability from txdata (8bit interface) and partner ability from rxdata (8bit interface).

Auto Negotiation exchange device ability to achieve best configuration to determine the link speed and feature. Link synchronization must be acquired first before the Auto Negotiation process can be completed.

9/94/ANProcess.png

Example 1: TSE IP with 1000Base-X PCS is connected in loopback mode and the Auto Negotiation failed and could not transmit/receive any Ethernet frame.

1. Check the Link and Auto Negotiation status.

2. Analyze the data that is being transmit and receive.

8/89/Ancs1.png

The configuration /C/ with 0x0000 is observed on the transceiver interface. This mean the Auto negotiation process is still in the early stage. Simulation time ~50us, too short for 1000Base-X AN (Link Timer = 10ms).

3. Speed Up the Auto Negotiation process.

• Specification Requirement: 1000Base-X Link Timer = 10ms (Default TSE Value), SGMII Link Timer = 1.6us

• For faster simulation time, set the link timer to 2us (Word offset 0x12 = 0xFD, Word offset 0x13 = 0x00)

• Restart the Auto Negotiation process (bit 9 in PCS Control Register)

7/73/Ansim.png

Example 2: Auto Negotiation completed but 2 devices run at different speed. It was due to 2 SGMII PCS are configured with Auto Negotiation in MAC mode. In SGMII AN, one PCS must be in MAC mode and the other in PHY mode.

0/08/Ancs4.png

2/20/Ancs5.png

Example 3: Auto Negotiation succeeded with mismatch ability advertised.

It happened that "SGMII bridge" option was enabled in parameter setting but SGMII ENA bit of IF_MODE register was set to '0'. The SGMII mode does not disabled if SGMII bridge is enabled in the parameter setting. Hence, Auto Negotiation was done in SGMII mode instead of 1000BASE-X mode. dev_ability and partner_ability registers do not take effect in SGMII mode.

Auto Negotiation Monitoring Points

//--- *U_RCAPS|clk domain ------------------------

//--- RX PCS Input Signals

*U_RCAPS|rx_sync

*U_RCAPS|frame

*U_RCAPS|kcahr

*U_RCAPS|char_err

*U_RCAPS|xmit_data

*U_RCAPS|carrier_detect

//--- RX PCS Output Signals

*U_RCAPS|receiver

*U_RCAPS|idle_ena

*U_RCAPS|rx_invalid

*U_RCAPS|gmii_dv

*U_RCAPS|gmii_err

*U_RCAPS|gmii_data

//--- RX Sync State Machine

*U_RCAPS|state.STM_TYP_RX_FAULT

//--- RX PCS State Machine Part A

*U_RCAPS|state.STM_TYP_K_WAIT

*U_RCAPS|state.STM_TYP_RX_K

*U_RCAPS|state.STM_TYP_AN_CB

*U_RCAPS|state.STM_TYP_AN_CC

*U_RCAPS|state.STM_TYP_AN_CD

*U_RCAPS|state.STM_TYP_RX_INVAL

*U_RCAPS|state.STM_TYP_IDLE_D

*U_RCAPS|state.STM_TYP_FALSE_CAR

//--- RX PCS State Machine Part B

*U_RCAPS|state.STM_TYP_FRM

*U_RCAPS|state.STM_TYP_FRM_START

*U_RCAPS|state.STM_TYP_FRM_END1

*U_RCAPS|state.STM_TYP_FRM_END2

*U_RCAPS|state.STM_TYP_FRM_END_EXTEND1

*U_RCAPS|state.STM_TYP_FRM_END_EXTEND2

*U_RCAPS|state.STM_TYP_EARLY_END

*U_RCAPS|state.STM_TYP_EARLY_END_EXTEND1

*U_RCAPS|state.STM_TYP_EARLY_END_EXTEND2

*U_RCAPS|state.STM_TYP_EARLY_END_EXTEND3

//--- Auto-Negotiation State Machine

*U_AUTONEG|state.STM_TYP_ABILITY_DETECT

*U_AUTONEG|state.STM_TYP_ACK_DETECT

*U_AUTONEG|state.STM_TYP_AUTONEG_ENA

*U_AUTONEG|state.STM_TYP_AUTONEG_RESTART

*U_AUTONEG|state.STM_TYP_COMPLETE_ACK

*U_AUTONEG|state.STM_TYP_IDLE_DETECT

*U_AUTONEG|state.STM_TYP_LINK_OK

*U_AUTONEG|state.STM_TYP_NO_AN_LINK

//--- Link Status LED

*u_mac|led_an

*u_mac|led_link

*u_mac|led_panel_link

*u_mac|led_char_err

//--- *U_TCAPS|clk domain ------------------------

//--- TX PCS Signals

*U_TCAPS|tx_ena

*U_TCAPS|tx_idle

*U_TCAPS|gmii_dv

*U_TCAPS|gmii_ctl

*U_TCAPS|gmii_data

*U_TCAPS|disparity

*U_TCAPS|frame

//--- TX PCS Code-group State Machine

*U_TCAPS|state.STM_TYP_CF_C1A

*U_TCAPS|state.STM_TYP_CF_C1B

*U_TCAPS|state.STM_TYP_CF_C1C

*U_TCAPS|state.STM_TYP_CF_C1D

*U_TCAPS|state.STM_TYP_CF_C2A

*U_TCAPS|state.STM_TYP_CF_C2B

*U_TCAPS|state.STM_TYP_CF_C2C

*U_TCAPS|state.STM_TYP_CF_C2D

//--- TX PCS Ordered_set State Machine

*U_TCAPS|state.STM_TYP_IDLE

*U_TCAPS|state.STM_TYP_FRM

*U_TCAPS|state.STM_TYP_FRM_DATA_ERR

*U_TCAPS|state.STM_TYP_FRM_START

*U_TCAPS|state.STM_TYP_FRM_START_ERR

*U_TCAPS|state.STM_TYP_FRM_END

*U_TCAPS|state.STM_TYP_FRM_END2

*U_TCAPS|state.STM_TYP_FRM_END3

//--- *U_REG|reg_clk domain ----------------------

//--- PCS Register

// Register Read/Write Data

*U_REG|data_in

*U_REG|data_out

// Word Offset 0x00 Control Register

*U_REG|unidirectional_enable

*U_REG|an_restart

*U_REG|an_enable

*U_REG|loopback_ena

*U_REG|sw_reset

// Word Offset 0x01 Status Register

*U_REG|link_status_reg2

*U_REG|an_done_reg2

// Word Offset 0x04 Device Ability Register

*U_REG|an_ability

// Word Offset 0x05 Link Partner Ability Register

*U_REG|lp_ability

// word Offset 0x12 to 0x13 Link Timer Register

*U_REG|link_timer_reg

// word Offset 0x14 IF_Mode Register

*U_REG|if_mode

*U_REG|use_sgmii

*U_REG|use_sgmii_an

*U_REG|sgmii_phy_mode

PMA Case Study

To investigate on PMA related issue,

1. Make sure PMA is out of reset and Reset sequence must be follow the device handbook (tx_digitalreset, tx_analogreset, tx_cal_busy, rx_digitalreset,rx_analogreset, rx_cal_busy).

2. Check the Transceiver interface to make sure pll is locked and rxfreq_lock/rxlock_todata/rx_lock_to_ref are asserted.

3. Make sure link synchronization is up (rx_syncstatus is asserted). Check the 8 bit data (rx_data) + 1bit control (rx_ctrlena) to make sure the received pattern is correct if the link down.

External PHY Case Study

To investigate on External PHY related issue,

1. Make sure external PHY out of reset.

2. Make sure FPGA TX transmit correct Idle,C1,C2 order set at both parallel data 8 bit/10 bit interface and serial interface.

Disclaimer

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